otsdaq_prepmodernization  v2_05_00
INFO_FIFO_0_pkg.vhd
1 --------------------------------------------------------------------------------
2 --
3 -- FIFO Generator Core Demo Testbench
4 --
5 --------------------------------------------------------------------------------
6 --
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52 --------------------------------------------------------------------------------
53 --
54 -- Filename: INFO_FIFO_0_pkg.vhd
55 --
56 -- Description:
57 -- This is the demo testbench package file for FIFO Generator core.
58 --
59 --------------------------------------------------------------------------------
60 -- Library Declarations
61 --------------------------------------------------------------------------------
62 LIBRARY IEEE;
63 USE IEEE.STD_LOGIC_1164.ALL;
64 USE ieee.std_logic_arith.ALL;
65 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
66 
67 PACKAGE INFO_FIFO_0_pkg IS
68 
69  FUNCTION divroundup (
70  data_value : INTEGER;
71  divisor : INTEGER)
72  RETURN INTEGER;
73  ------------------------
74  FUNCTION if_then_else (
75  condition : BOOLEAN;
76  true_case : INTEGER;
77  false_case : INTEGER)
78  RETURN INTEGER;
79  ------------------------
80  FUNCTION if_then_else (
81  condition : BOOLEAN;
82  true_case : STD_LOGIC;
83  false_case : STD_LOGIC)
84  RETURN STD_LOGIC;
85  ------------------------
86  FUNCTION if_then_else (
87  condition : BOOLEAN;
88  true_case : TIME;
89  false_case : TIME)
90  RETURN TIME;
91  ------------------------
92  FUNCTION log2roundup (
93  data_value : INTEGER)
94  RETURN INTEGER;
95  ------------------------
96  FUNCTION hexstr_to_std_logic_vec(
97  arg1 : string;
98  size : integer )
99  RETURN std_logic_vector;
100  ------------------------
101  COMPONENT INFO_FIFO_0_rng IS
102  GENERIC (WIDTH : integer := 8;
103  SEED : integer := 3);
104  PORT (
105  CLK : IN STD_LOGIC;
106  RESET : IN STD_LOGIC;
107  ENABLE : IN STD_LOGIC;
108  RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
109  );
110  END COMPONENT;
111  ------------------------
112 
113  COMPONENT INFO_FIFO_0_dgen IS
114  GENERIC (
115  C_DIN_WIDTH : INTEGER := 32;
116  C_DOUT_WIDTH : INTEGER := 32;
117  C_CH_TYPE : INTEGER := 0;
118  TB_SEED : INTEGER := 2
119  );
120  PORT (
121  RESET : IN STD_LOGIC;
122  WR_CLK : IN STD_LOGIC;
123  PRC_WR_EN : IN STD_LOGIC;
124  FULL : IN STD_LOGIC;
125  WR_EN : OUT STD_LOGIC;
126  WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
127  );
128  END COMPONENT;
129  ------------------------
130 
131  COMPONENT INFO_FIFO_0_dverif IS
132  GENERIC(
133  C_DIN_WIDTH : INTEGER := 0;
134  C_DOUT_WIDTH : INTEGER := 0;
135  C_USE_EMBEDDED_REG : INTEGER := 0;
136  C_CH_TYPE : INTEGER := 0;
137  TB_SEED : INTEGER := 2
138  );
139  PORT(
140  RESET : IN STD_LOGIC;
141  RD_CLK : IN STD_LOGIC;
142  PRC_RD_EN : IN STD_LOGIC;
143  EMPTY : IN STD_LOGIC;
144  DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
145  RD_EN : OUT STD_LOGIC;
146  DOUT_CHK : OUT STD_LOGIC
147  );
148  END COMPONENT;
149  ------------------------
150 
151  COMPONENT INFO_FIFO_0_pctrl IS
152  GENERIC(
153  AXI_CHANNEL : STRING := "NONE";
154  C_APPLICATION_TYPE : INTEGER := 0;
155  C_DIN_WIDTH : INTEGER := 0;
156  C_DOUT_WIDTH : INTEGER := 0;
157  C_WR_PNTR_WIDTH : INTEGER := 0;
158  C_RD_PNTR_WIDTH : INTEGER := 0;
159  C_CH_TYPE : INTEGER := 0;
160  FREEZEON_ERROR : INTEGER := 0;
161  TB_STOP_CNT : INTEGER := 2;
162  TB_SEED : INTEGER := 2
163  );
164  PORT(
165  RESET_WR : IN STD_LOGIC;
166  RESET_RD : IN STD_LOGIC;
167  WR_CLK : IN STD_LOGIC;
168  RD_CLK : IN STD_LOGIC;
169  FULL : IN STD_LOGIC;
170  EMPTY : IN STD_LOGIC;
171  ALMOST_FULL : IN STD_LOGIC;
172  ALMOST_EMPTY : IN STD_LOGIC;
173  DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
174  DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
175  DOUT_CHK : IN STD_LOGIC;
176  PRC_WR_EN : OUT STD_LOGIC;
177  PRC_RD_EN : OUT STD_LOGIC;
178  RESET_EN : OUT STD_LOGIC;
179  SIM_DONE : OUT STD_LOGIC;
180  STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
181  );
182  END COMPONENT;
183  ------------------------
184  COMPONENT INFO_FIFO_0_synth IS
185  GENERIC(
186  FREEZEON_ERROR : INTEGER := 0;
187  TB_STOP_CNT : INTEGER := 0;
188  TB_SEED : INTEGER := 1
189  );
190  PORT(
191  CLK : IN STD_LOGIC;
192  RESET : IN STD_LOGIC;
193  SIM_DONE : OUT STD_LOGIC;
194  STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
195  );
196  END COMPONENT;
197  ------------------------
198  COMPONENT INFO_FIFO_0_exdes IS
199  PORT (
200  CLK : IN std_logic;
201  SRST : IN std_logic;
202  WR_EN : IN std_logic;
203  RD_EN : IN std_logic;
204  DIN : IN std_logic_vector(16-1 DOWNTO 0);
205  DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
206  FULL : OUT std_logic;
207  EMPTY : OUT std_logic);
208 
209  END COMPONENT;
210  ------------------------
211 
212 
213 END INFO_FIFO_0_pkg;
214 
215 
216 
217 PACKAGE BODY _INFO_FIFO_0_pkg IS
218 
219  FUNCTION divroundup (
220  data_value : INTEGER;
221  divisor : INTEGER)
222  RETURN INTEGER IS
223  VARIABLE div : INTEGER;
224  BEGIN
225  div := data_value/divisor;
226  IF ( (data_value MOD divisor) /= 0) THEN
227  div := div+1;
228  END IF;
229  RETURN div;
230  END divroundup;
231  ---------------------------------
232  FUNCTION if_then_else (
233  condition : BOOLEAN;
234  true_case : INTEGER;
235  false_case : INTEGER)
236  RETURN INTEGER IS
237  VARIABLE retval : INTEGER := 0;
238  BEGIN
239  IF condition=false THEN
240  retval:=false_case;
241  ELSE
242  retval:=true_case;
243  END IF;
244  RETURN retval;
245  END if_then_else;
246  ---------------------------------
247  FUNCTION if_then_else (
248  condition : BOOLEAN;
249  true_case : STD_LOGIC;
250  false_case : STD_LOGIC)
251  RETURN STD_LOGIC IS
252  VARIABLE retval : STD_LOGIC := '0';
253  BEGIN
254  IF condition=false THEN
255  retval:=false_case;
256  ELSE
257  retval:=true_case;
258  END IF;
259  RETURN retval;
260  END if_then_else;
261  ---------------------------------
262  FUNCTION if_then_else (
263  condition : BOOLEAN;
264  true_case : TIME;
265  false_case : TIME)
266  RETURN TIME IS
267  VARIABLE retval : TIME := 0 ps;
268  BEGIN
269  IF condition=false THEN
270  retval:=false_case;
271  ELSE
272  retval:=true_case;
273  END IF;
274  RETURN retval;
275  END if_then_else;
276  -------------------------------
277  FUNCTION log2roundup (
278  data_value : INTEGER)
279  RETURN INTEGER IS
280 
281  VARIABLE width : INTEGER := 0;
282  VARIABLE cnt : INTEGER := 1;
283  BEGIN
284  IF (data_value <= 1) THEN
285  width := 1;
286  ELSE
287  WHILE (cnt < data_value) LOOP
288  width := width + 1;
289  cnt := cnt *2;
290  END LOOP;
291  END IF;
292 
293  RETURN width;
294  END log2roundup;
295  ------------------------------------------------------------------------------
296  -- hexstr_to_std_logic_vec
297  -- This function converts a hex string to a std_logic_vector
298  ------------------------------------------------------------------------------
299  FUNCTION hexstr_to_std_logic_vec(
300  arg1 : string;
301  size : integer )
302  RETURN std_logic_vector IS
303  VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
304  VARIABLE bin : std_logic_vector(3 DOWNTO 0);
305  VARIABLE index : integer := 0;
306  BEGIN
307  FOR i IN arg1'reverse_range LOOP
308  CASE arg1(i) IS
309  WHEN '0' => bin := (OTHERS => '0');
310  WHEN '1' => bin := (0 => '1', OTHERS => '0');
311  WHEN '2' => bin := (1 => '1', OTHERS => '0');
312  WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
313  WHEN '4' => bin := (2 => '1', OTHERS => '0');
314  WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
315  WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
316  WHEN '7' => bin := (3 => '0', OTHERS => '1');
317  WHEN '8' => bin := (3 => '1', OTHERS => '0');
318  WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
319  WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
320  WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
321  WHEN 'B' => bin := (2 => '0', OTHERS => '1');
322  WHEN 'b' => bin := (2 => '0', OTHERS => '1');
323  WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
324  WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
325  WHEN 'D' => bin := (1 => '0', OTHERS => '1');
326  WHEN 'd' => bin := (1 => '0', OTHERS => '1');
327  WHEN 'E' => bin := (0 => '0', OTHERS => '1');
328  WHEN 'e' => bin := (0 => '0', OTHERS => '1');
329  WHEN 'F' => bin := (OTHERS => '1');
330  WHEN 'f' => bin := (OTHERS => '1');
331  WHEN OTHERS =>
332  FOR j IN 0 TO 3 LOOP
333  bin(j) := 'X';
334  END LOOP;
335  END CASE;
336  FOR j IN 0 TO 3 LOOP
337  IF (index*4)+j < size THEN
338  result((index*4)+j) := bin(j);
339  END IF;
340  END LOOP;
341  index := index + 1;
342  END LOOP;
343  RETURN result;
344  END hexstr_to_std_logic_vec;
345 
346 END INFO_FIFO_0_pkg;