2 use ieee.std_logic_1164.
ALL;
3 use ieee.numeric_std.
ALL;
4 use ieee.std_logic_misc.
ALL;
7 use UNISIM.Vcomponents.
ALL;
23 --PHY_RXER : in std_logic;
24 --USER_CLOCK : in std_logic;
26 --PHY_RESET : out std_logic;
28 PHY_TXCTL_TXEN : out ;
45 architecture BEHAVIORAL
of top is
48 attribute BOX_TYPE : ;
49 attribute IOSTANDARD : ;
50 attribute CAPACITANCE : ;
53 attribute IBUF_LOW_PWR : ;
55 signal b_data : (63 downto 0);
57 signal GMII_RXD_0_sig : (7 downto 0);
58 signal GMII_RX_DV_0_sig : ;
59 signal GMII_RX_ER_0_sig : ;
60 signal GTX_CLK_0_sig : ;
62 signal CLK15NS, CLK15NS_sig : ;
64 signal gec_mac, gec_user_src_mac : (47 downto 0);
65 signal gec_port, gec_user_src_port : (15 downto 0);
66 signal gec_addrs, gec_user_src_addrs : (7 downto 0);
68 signal gec_user_src_capture : ;
74 signal PHY_TXD_sig : (7 downto 0);
75 signal PHY_TXEN_sig : ;
76 signal PHY_TXER_sig : ;
77 signal psi_status : (63 downto 0);
80 signal rx_addr : (31 downto 0);
81 signal rx_data : (63 downto 0);
83 signal secondary_clk, secondary_clk_sig : ;
84 signal tx_data : (63 downto 0);
89 attribute mark_debug : ;
90 attribute mark_debug of MASTER_CLK : signal is "true";
91 attribute mark_debug of secondary_clk : signal is "true";
92 attribute mark_debug of PHY_TXD_sig : signal is "true";
93 attribute mark_debug of PHY_TXEN_sig : signal is "true";
94 attribute mark_debug of rx_wren : signal is "true";
95 attribute mark_debug of CLK15NS : signal is "true";
97 -- attribute mark_debug of GMII_RXD_0_sig : signal is "true";
98 -- attribute mark_debug of GMII_RX_DV_0_sig : signal is "true";
99 -- attribute mark_debug of rx_addr : signal is "true";
100 -- attribute mark_debug of rx_data : signal is "true";
108 attribute IOSTANDARD of OBUF : component is "DEFAULT";
109 attribute CAPACITANCE of OBUF : component is "DONT_CARE";
110 attribute SLEW of OBUF : component is "SLOW";
111 attribute DRIVE of OBUF : component is "12";
112 attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
118 attribute IOSTANDARD of IBUF : component is "DEFAULT";
119 attribute CAPACITANCE of IBUF : component is "DONT_CARE";
120 attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
123 -- synopsys translate_off
124 generic( IBUF_LOW_PWR : := TRUE);
125 -- synopsys translate_on
129 attribute IOSTANDARD of IBUFG : component is "DEFAULT";
130 attribute CAPACITANCE of IBUFG : component is "DONT_CARE";
131 attribute IBUF_LOW_PWR of IBUFG : component is "TRUE";
132 attribute BOX_TYPE of IBUFG : component is "BLACK_BOX";
139 attribute BOX_TYPE of BUFG : component is "BLACK_BOX";
142 port ( slow_clk :
in ;
153 reset_n <= not reset;
156 -- reset_ibuf : IBUF -- SW3 on board is active high
157 -- port map (I=>GPIO_SW_W, O=>reset_btn);
158 -- user_led1: OBUF -- LED display of RESET
159 -- port map (I=>reset, O=>PZ_ULED_1);
163 eth_interface :
entity work.Ethernet_Interface
164 port map (b_data
(63 downto 0)=>b_data
(63 downto 0),
165 b_data_we =>b_data_we,
166 PHY_RXD
(7 downto 0)=>GMII_RXD_0_sig
(7 downto 0),
167 PHY_RX_DV =>GMII_RX_DV_0_sig,
168 PHY_RX_ER =>GMII_RX_ER_0_sig,
169 MASTER_CLK =>MASTER_CLK,
170 reset_in =>reset_btn,
172 tx_data
(63 downto 0)=>tx_data
(63 downto 0),
174 TX_CLK =>GTX_CLK_0_sig,
175 PHY_TXD
(7 downto 0)=>PHY_TXD_sig
(7 downto 0),
176 PHY_TX_EN =>PHY_TXEN_sig,
177 PHY_TX_ER =>PHY_TXER_sig,
178 rx_addr
(31 downto 0)=>rx_addr
(31 downto 0),
179 rx_data
(63 downto 0)=>rx_data
(63 downto 0),
188 -- start data gen block
189 dataGenGen : for i in 0 to 0 generate
190 signal reg_cnt : (63 downto 0) := (others => '0');
-- 1s is infinite
191 signal reg_rate : (63 downto 0) := (others => '0');
-- delay between 8 clock periods
193 signal cnt : (2 downto 0) := (others => '0');
194 signal delay_cnt : (63 downto 0) := (others => '0');
195 signal data_cnt : (31 downto 0) := (others => '0');
199 if (rising_edge(MASTER_CLK)) then
204 if (rx_wren = '1') then
205 if ((rx_addr) = x"1001") then --reg_cnt
206 reg_cnt <= (rx_data);
207 elsif ((rx_addr) = x"1002") then --reg_rate
208 reg_rate <= (rx_data);
210 delay_cnt <= (others => '0');
--reset delay and execute burst write
214 if (cnt = 0) then --count groups of 8 with wrap around
215 delay_cnt <= delay_cnt + 1;
217 if (delay_cnt = reg_rate and reg_cnt /= 0) then
218 delay_cnt <= (others => '0');
--reset delay and execute burst write
219 b_data(63 downto 32) <= (data_cnt);
220 b_data(31 downto 0) <= tx_data(31 downto 0);
-- last saved write
222 data_cnt <= data_cnt + 1;
224 if ( and_reduce((reg_cnt)) /= '1' ) then --count down pulses, if not infinite
225 reg_cnt <= reg_cnt -
1;
234 -- end data gen block
237 makeSlowClock : for i in 0 to 0 generate
238 signal cnt : (4 downto 0) := (others => '0');
240 secondary_clk_sig <= cnt(4);
-- 32 times slower clock than MASTER_CLK
241 CLK15NS_sig <= cnt(0);
-- 2 times slower clock than MASTER_CLK
244 if (rising_edge(MASTER_CLK)) then
251 port map (I =>secondary_clk_sig, O =>secondary_clk
);
254 port map (I =>CLK15NS_sig, O =>CLK15NS
);
256 -- tx_data for reads.. rx_address(31:0) | rx_data(31:0)
257 tx_data(63 downto 32) <= rx_addr(31 downto 0);
260 if (rising_edge(MASTER_CLK) and rx_wren='1') then
261 tx_data(15 downto 0) <= rx_data(15 downto 0);
267 if (rising_edge(CLK15NS)) then
268 tx_data(31 downto 24) <= ((tx_data(31 downto 24)) + 1);
272 process(secondary_clk)
274 if (rising_edge(secondary_clk)) then
275 tx_data(23 downto 16) <= ((tx_data(23 downto 16)) + 1);
279 -----------------------
280 ----------------------- IBUF 's
282 IBUF_PHY_RXDV : IBUF
port map (I =>PHY_RXCTL_RXDV, O =>GMII_RX_DV_0_sig
);
284 --removed by script (others => '0'); -- for RGMII or SGMII
286 IBUF_PHY_RXD7 : IBUF
port map (I =>PHY_RXD7, O =>GMII_RXD_0_sig
(7));
287 IBUF_PHY_RXD6 : IBUF
port map (I =>PHY_RXD6, O =>GMII_RXD_0_sig
(6));
288 IBUF_PHY_RXD5 : IBUF
port map (I =>PHY_RXD5, O =>GMII_RXD_0_sig
(5));
289 IBUF_PHY_RXD4 : IBUF
port map (I =>PHY_RXD4, O =>GMII_RXD_0_sig
(4));
290 IBUF_PHY_RXD3 : IBUF
port map (I =>PHY_RXD3, O =>GMII_RXD_0_sig
(3));
291 IBUF_PHY_RXD2 : IBUF
port map (I =>PHY_RXD2, O =>GMII_RXD_0_sig
(2));
292 IBUF_PHY_RXD1 : IBUF
port map (I =>PHY_RXD1, O =>GMII_RXD_0_sig
(1));
293 IBUF_PHY_RXD0 : IBUF
port map (I =>PHY_RXD0, O =>GMII_RXD_0_sig
(0));
295 GMII_RX_ER_0_sig <= '0';
297 IBUF_PHY_RXCLK : IBUFG
port map (I =>PHY_RXCLK, O =>MASTER_CLK
);
299 -----------------------
300 ----------------------- OBUF 's
302 --OBUF_PHY_RESET : OBUF port map (I=>'1', O=>PHY_RESET); --hold not reset
304 OBUF_PHY_TXER : OBUF
port map (I =>PHY_TXER_sig, O =>PHY_TXER
);
306 OBUF_PHY_TXEN : OBUF
port map (I =>PHY_TXEN_sig, O =>PHY_TXCTL_TXEN
);
308 OBUF_PHY_TXCLK : OBUF
port map (I =>GTX_CLK_0_sig, O =>PHY_TXC_GTXCLK
);
310 OBUF_PHY_TXD7 : OBUF
port map (I =>PHY_TXD_sig
(7), O =>PHY_TXD7
);
311 OBUF_PHY_TXD6 : OBUF
port map (I =>PHY_TXD_sig
(6), O =>PHY_TXD6
);
312 OBUF_PHY_TXD5 : OBUF
port map (I =>PHY_TXD_sig
(5), O =>PHY_TXD5
);
313 OBUF_PHY_TXD4 : OBUF
port map (I =>PHY_TXD_sig
(4), O =>PHY_TXD4
);
314 OBUF_PHY_TXD3 : OBUF
port map (I =>PHY_TXD_sig
(3), O =>PHY_TXD3
);
315 OBUF_PHY_TXD2 : OBUF
port map (I =>PHY_TXD_sig
(2), O =>PHY_TXD2
);
316 OBUF_PHY_TXD1 : OBUF
port map (I =>PHY_TXD_sig
(1), O =>PHY_TXD1
);
317 OBUF_PHY_TXD0 : OBUF
port map (I =>PHY_TXD_sig
(0), O =>PHY_TXD0
);