|
otsdaq_prepmodernization
v2_05_00
|
Libraries | |
| ieee | |
| UNISIM | |
Use Clauses | |
| ieee.std_logic_1164.all | |
| ieee.numeric_std.all | |
| UNISIM.Vcomponents.all | |
Ports | |
| addra | in std_logic_vector ( 5 downto 0 ) |
| addrb | in std_logic_vector ( 5 downto 0 ) |
| clka | in std_logic |
| clkb | in std_logic |
| dina | in std_logic_vector ( 63 downto 0 ) |
| dinb | in std_logic_vector ( 63 downto 0 ) |
| wea | in std_logic_vector ( 0 downto 0 ) |
| web | in std_logic_vector ( 0 downto 0 ) |
| douta | out std_logic_vector ( 63 downto 0 ) |
| doutb | out std_logic_vector ( 63 downto 0 ) |
Definition at line 24 of file blk_mem_gen_v2_6.vhd.