|
otsdaq_prepmodernization
v2_05_00
|
Libraries | |
| IEEE | |
Use Clauses | |
| IEEE.std_logic_1164.all | |
| IEEE.NUMERIC_STD.all | |
| work.params_package.all | |
Ports | |
| clock | in STD_LOGIC |
| crc_err_flag | in STD_LOGIC |
| reset | in STD_LOGIC |
| rx_data_fifo_full | in STD_LOGIC |
| rx_data_fifo_rd_data | in STD_LOGIC_VECTOR ( 63 downto 0 ) |
| rx_info_fifo_empty | in STD_LOGIC |
| rx_info_fifo_full | in STD_LOGIC |
| rx_info_fifo_rd_data | in STD_LOGIC_VECTOR ( 15 downto 0 ) |
| tx_info_fifo_full | in STD_LOGIC |
| user_ready | in STD_LOGIC |
| user_rx_valid_out | in STD_LOGIC |
| clear_crc_err_flag | out STD_LOGIC |
| ram_addr | out STD_LOGIC_VECTOR ( 63 downto 0 ) |
| ram_rden | out STD_LOGIC |
| ram_wdata | out STD_LOGIC_VECTOR ( 63 downto 0 ) |
| ram_wren | out STD_LOGIC |
| rx_data_fifo_rden | out STD_LOGIC |
| Rx_FIFO_Reset | out STD_LOGIC |
| rx_info_fifo_rden | out STD_LOGIC |
| tx_data_fifo_wren | out STD_LOGIC |
| Tx_FIFO_Reset | out STD_LOGIC |
| tx_info_fifo_wr_data | out STD_LOGIC_VECTOR ( 15 downto 0 ) |
| tx_info_fifo_wren | out STD_LOGIC |
Definition at line 26 of file ram_comm_dec.vhd.