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otsdaq_prepmodernization
v2_05_00
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Libraries | |
| ieee | |
| XilinxCoreLib | |
Use Clauses | |
| ieee.std_logic_1164.all | |
Ports | |
| wr_clk | in STD_LOGIC |
| rd_clk | in STD_LOGIC |
| din | in STD_LOGIC_VECTOR ( 15 downto 0 ) |
| wr_en | in STD_LOGIC |
| rd_en | in STD_LOGIC |
| dout | out STD_LOGIC_VECTOR ( 63 downto 0 ) |
| full | out STD_LOGIC |
| overflow | out STD_LOGIC |
| empty | out STD_LOGIC |
| valid | out STD_LOGIC |
Definition at line 43 of file ADC_FIFO.vhd.