otsdaq_prepmodernization  v2_05_00
GEC_TX_SEQ_CTL_8.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : GEC_TX_SEQ_CTL_8
4 -- Design : ethernet_controller
5 -- Author : aprosser
6 -- Company : CD_CEPA_ESE
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : c:\HDL_Designs\dig_gec\ethernet_controller\compile\GEC_TX_SEQ_CTL_8.vhd
11 -- Generated : 03/20/09 15:19:36
12 -- From : c:/HDL_Designs/dig_gec/ethernet_controller/src/GEC_TX_SEQ_CTL_8.asf
13 -- By : FSM2VHDL ver. 5.0.5.6
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_arith.all;
24 use IEEE.std_logic_unsigned.all;
25 use params_package.all;
26 
27 entity GEC_TX_SEQ_CTL_8 is
28  port (
29  block_en: in STD_LOGIC;
30  clk: in STD_LOGIC;
31  data_fifo_empty: in STD_LOGIC;
32  data_fifo_rd_data: in STD_LOGIC_VECTOR (63 downto 0);
33  data_fifo_rderr: in STD_LOGIC;
34  delay_count: in STD_LOGIC;
35  gec_user_busy: in STD_LOGIC;
36  gec_user_tx_enable_out: in STD_LOGIC;
37  info_fifo_empty: in STD_LOGIC;
38  info_fifo_rd_data: in STD_LOGIC_VECTOR (15 downto 0);
39  info_fifo_rderr: in STD_LOGIC;
40  reset_n: in STD_LOGIC;
41  clear_delay_count: out STD_LOGIC;
42  data_fifo_rden: out STD_LOGIC;
43  data_fifo_rden_en: out STD_LOGIC;
44  gec_user_trigger: out STD_LOGIC;
45  gec_user_tx_data_in: out STD_LOGIC_VECTOR (7 downto 0);
46  gec_user_tx_size_in: out STD_LOGIC_VECTOR (10 downto 0);
47  info_fifo_rden: out STD_LOGIC;
48  start_delay_count: out STD_LOGIC);
49 end GEC_TX_SEQ_CTL_8;
50 
51 architecture GEC_TX_SEQ_CTL_8 of GEC_TX_SEQ_CTL_8 is
52 
53 -- diagram signals declarations
54 signal byte_count: STD_LOGIC_VECTOR (2 downto 0);
55 signal data_fifo_rd_data_reg: STD_LOGIC_VECTOR (63 downto 0);
56 signal q_w_count: STD_LOGIC_VECTOR (7 downto 0);
57 signal seq_count: STD_LOGIC_VECTOR (7 downto 0);
58 signal tx_data_count: STD_LOGIC_VECTOR (10 downto 0);
59 
60 -- BINARY ENCODED state machine: Sreg0
61 attribute enum_encoding: string;
62 type Sreg0_type is (
63  idle, enabled, chk_busy, txmtdone, data_rdy_read_Ififo, trgrd, data_rdy_savecount, txmt_xmiting, S1, S2, txmt_S3, S4, S5
64 );
65 attribute enum_encoding of Sreg0_type: type is
66  "0000 " & -- idle
67  "0001 " & -- enabled
68  "0010 " & -- chk_busy
69  "0011 " & -- txmtdone
70  "0100 " & -- data_rdy_read_Ififo
71  "0101 " & -- trgrd
72  "0110 " & -- data_rdy_savecount
73  "0111 " & -- txmt_xmiting
74  "1000 " & -- S1
75  "1001 " & -- S2
76  "1010 " & -- txmt_S3
77  "1011 " & -- S4
78  "1100" ; -- S5
79 
80 signal Sreg0: Sreg0_type;
81 
82 attribute state_vector: string;
83 attribute state_vector of GEC_TX_SEQ_CTL_8: architecture is "Sreg0";
84 
85 begin
86 
87 
88 ----------------------------------------------------------------------
89 -- Machine: Sreg0
90 ----------------------------------------------------------------------
91 Sreg0_machine: process (clk)
92 begin
93  if clk'event and clk = '1' then
94  if reset_n = '0' then
95  Sreg0 <= idle;
96  -- Set default values for outputs, signals and variables
97  -- ...
98  gec_user_trigger <= '0';
99  gec_user_tx_size_in <= v_11_0;
100  q_w_count <= v_8_0;
101  tx_data_count <= v_11_0;
102  info_fifo_rden <= '0';
103  data_fifo_rden <= '0';
104  data_fifo_rden_en <= '0';
105  data_fifo_rd_data_reg <= v_64_0;
106  byte_count <= "000";
107  start_delay_count <= '0';
108  clear_delay_count <= '0';
109  else
110  -- Set default values for outputs, signals and variables
111  -- ...
112  case Sreg0 is
113  when idle =>
114  if block_en = '0' then
115  Sreg0 <= idle;
116  elsif block_en = '1' then
117  Sreg0 <= enabled;
118  end if;
119  when enabled =>
120  if block_en = '0' then
121  Sreg0 <= idle;
122  elsif (info_fifo_empty = '0' and block_en = '1') and
123  delay_count = '0' then -- FIFO has an entry and no more delay needed
124  Sreg0 <= data_rdy_read_Ififo;
125  clear_delay_count <= '1';
126  info_fifo_rden <= '1';
127  -- Read the info word
128  byte_count <= "000";
129  elsif (info_fifo_empty = '1' and block_en = '1') or
130  delay_count = '1' then -- FIFO is empty or delay not complete
131  Sreg0 <= enabled;
132  end if;
133  when chk_busy =>
134  if gec_user_busy = '0' then
135  Sreg0 <= trgrd;
136  gec_user_trigger <= '1';
137  -- GEC not busy
138  -- assert trigger to GEC
139  if (tx_data_count /= v_11_2) then
140  data_fifo_rd_data_reg <= data_fifo_rd_data;
141  -- prepare first quad word if there is one
142  end if;
143  elsif gec_user_busy = '1' then
144  Sreg0 <= chk_busy;
145  data_fifo_rden <= '0';
146  -- finished reading quad word fifo for first quad word
147  end if;
148  when txmtdone =>
149  if block_en = '1' then
150  Sreg0 <= enabled;
151  elsif block_en = '0' then
152  Sreg0 <= idle;
153  end if;
154  when trgrd =>
155  if gec_user_tx_enable_out = '0' then -- wait for enable tx reply
156  Sreg0 <= trgrd;
157  elsif gec_user_tx_enable_out = '1' then
158  Sreg0 <= S5;
159  gec_user_tx_data_in <= seq_count;
160  end if;
161  when S1 =>
162  Sreg0 <= S2;
163  tx_data_count <= tx_data_count + v_11_2;
164  -- add return code byte to
165  -- produce the final number of bytes
166  -- add sequence counter byte also
167  start_delay_count <= '1';
168  when S2 =>
169  Sreg0 <= S4;
170  gec_user_tx_size_in <= tx_data_count;
171  -- present byte count to GEC
172  if (tx_data_count /= v_11_2) then
173  -- read a quad word for initialization
174  data_fifo_rden_en <= '1';
175  data_fifo_rden <= '1';
176  end if;
177  when S4 =>
178  Sreg0 <= chk_busy;
179  data_fifo_rden <= '0';
180  start_delay_count <= '0';
181  when S5 =>
182  Sreg0 <= txmt_xmiting;
183  if (tx_data_count = v_11_2) then
184  data_fifo_rden_en <= '0';
185  -- turn off FIFO accesses early
186  -- only one byte is requested and
187  -- it has been preloaded (this should
188  -- not happen in loopback tests
189  else
190  -- update the data presented to the GEC
191  gec_user_tx_data_in <= data_fifo_rd_data(63 downto 56);
192  -- increment the byte count
193  byte_count <= "001";
194  end if;
195  -- decrement count of bytes;
196  -- user_tx_enable_out from the GEC is
197  -- enabling read operations on the data
198  -- FIFO
199  when data_rdy_read_Ififo =>
200  Sreg0 <= data_rdy_savecount;
201  info_fifo_rden <= '0';
202  -- terminate info word read
203  clear_delay_count <= '0';
204  when data_rdy_savecount =>
205  Sreg0 <= S1;
206  q_w_count <= info_fifo_rd_data(15 downto 8);
207  -- get number of quad words
208  gec_user_tx_data_in <= info_fifo_rd_data(7 downto 0);
209  -- assert the return code to the GEC
210  -- when Ryan's enable out signal goes high
211  -- the return code is there already
212  tx_data_count <= info_fifo_rd_data(15 downto 8) & "000";
213  -- compute number of bytes in quad words to be returned to PC
214  -- multiplies quad word count by 8
215  data_fifo_rden <= '0';
216  -- terminate first data word read
217  when txmt_xmiting =>
218  if tx_data_count = v_11_2 then
219  Sreg0 <= txmt_S3;
220  gec_user_trigger <= '0';
221  gec_user_tx_size_in <= v_11_0;
222  tx_data_count <= v_11_0;
223  info_fifo_rden <= '0';
224  data_fifo_rden <= '0';
225  data_fifo_rden_en <= '0';
226  elsif q_w_count /= v_8_0 then
227  Sreg0 <= txmt_xmiting;
228  case byte_count is
229  when "000" =>
230  byte_count <= byte_count + v_3_1;
231  gec_user_tx_data_in <= data_fifo_rd_data_reg(63 downto 56);
232  when "001" =>
233  byte_count <= byte_count + v_3_1;
234  gec_user_tx_data_in <= data_fifo_rd_data_reg(55 downto 48);
235  when "010" =>
236  byte_count <= byte_count + v_3_1;
237  gec_user_tx_data_in <= data_fifo_rd_data_reg(47 downto 40);
238  -- Read a new data quad word with plenty of time to spare
239  -- Jefferson did this to compensate for commenting
240  --out the action done when q_w_count =v_5_1
241  if (q_w_count > v_5_1)then
242  data_fifo_rden <= '1';
243  end if;
244  when "011" =>
245  byte_count <= byte_count + v_3_1;
246  gec_user_tx_data_in <= data_fifo_rd_data_reg(39 downto 32);
247  -- Finish read a new data quad word with plenty of time to spare
248  data_fifo_rden <= '0';
249  when "100" =>
250  byte_count <= byte_count + v_3_1;
251  gec_user_tx_data_in <= data_fifo_rd_data_reg(31 downto 24);
252  -- at this point, the data_fifo_rd_data lines have the
253  -- next quad word sitting on them
254  when "101" =>
255  byte_count <= byte_count + v_3_1;
256  gec_user_tx_data_in <= data_fifo_rd_data_reg(23 downto 16);
257  when "110" =>
258  byte_count <= byte_count + v_3_1;
259  gec_user_tx_data_in <= data_fifo_rd_data_reg(15 downto 8);
260  when "111" =>
261  byte_count <= "000";
262  gec_user_tx_data_in <= data_fifo_rd_data_reg(7 downto 0);
263  -- read another quad word
264  data_fifo_rd_data_reg <= data_fifo_rd_data;
265  -- we latch the data into the internal register
266  -- data_fifo_rd_data_reg
267  q_w_count <= q_w_count - v_5_1;
268  -- decrement the quad word count after we process the 8 bytes
269  -- in a quad word
270  when others =>
271  byte_count <= "000";
272  --null;
273  end case;
274  elsif q_w_count = v_8_0 then
275  Sreg0 <= txmt_S3;
276  gec_user_trigger <= '0';
277  gec_user_tx_size_in <= v_11_0;
278  tx_data_count <= v_11_0;
279  info_fifo_rden <= '0';
280  data_fifo_rden <= '0';
281  data_fifo_rden_en <= '0';
282  --Jefferson commented this out because it caused only
283  -- the first case (when "000") was being run
284  -- I think it is because this is not a loop
285  --case byte_count is
286  -- when "000" =>
287  -- byte_count <= byte_count + v_3_1;
288  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(7 downto 0);
289  -- when "001" =>
290  -- byte_count <= byte_count + v_3_1;
291  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(15 downto 8);
292  -- when "010" =>
293  -- byte_count <= byte_count + v_3_1;
294  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(23 downto 16);
295  ---- Read a new data quad word with plenty of time to spare
296  ---- data_fifo_rden <= '1';
297  -- when "011" =>
298  -- byte_count <= byte_count + v_3_1;
299  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(31 downto 24);
300  ---- Finish read a new data quad word with plenty of time to spare
301  -- data_fifo_rden <= '0';
302  -- when "100" =>
303  -- byte_count <= byte_count + v_3_1;
304  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(39 downto 32);
305  ---- at this point, the data_fifo_rd_data lines have the
306  ---- next quad word sitting on them
307  -- when "101" =>
308  -- byte_count <= byte_count + v_3_1;
309  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(47 downto 40);
310  -- when "110" =>
311  -- byte_count <= byte_count + v_3_1;
312  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(55 downto 48);
313  -- when "111" =>
314  -- byte_count <= "000";
315  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(63 downto 56);
316  ---- read another quad word
317  ---- data_fifo_rd_data_reg <= data_fifo_rd_data;
318  ---- we latch the data into the internal register
319  ---- data_fifo_rd_data_reg
320  ---- q_w_count <= q_w_count - v_5_1;
321  ---- decrement the quad word count after we process the 8 bytes
322  ---- in a quad word
323  -- when others =>
324  -- byte_count <= "000";
325  -- --null;
326  --end case;
327  --
328  end if;
329  when txmt_S3 =>
330  Sreg0 <= txmtdone;
331  gec_user_trigger <= '0';
332  gec_user_tx_size_in <= v_11_0;
333  tx_data_count <= v_11_0;
334  info_fifo_rden <= '0';
335  data_fifo_rden <= '0';
336  data_fifo_rden_en <= '0';
337  gec_user_trigger <= '0';
338  gec_user_tx_size_in <= v_11_0;
339  tx_data_count <= v_11_0;
340  info_fifo_rden <= '0';
341  data_fifo_rden <= '0';
342  data_fifo_rden_en <= '0';
343  if (seq_count = v_8_255) then
344  seq_count <= v_8_0;
345  else
346  seq_count <= seq_count + v_8_1;
347  end if;
348 --vhdl_cover_off
349  when others =>
350  null;
351 --vhdl_cover_on
352  end case;
353  end if;
354  end if;
355 end process;
356 
357 end GEC_TX_SEQ_CTL_8;