otsdaq_prepmodernization  v2_05_00
udp_data_splicer.vhd
1 -- Author: Ryan Rivera, FNAL
2 
3 library IEEE;
4 use IEEE.std_logic_1164.all;
5 use IEEE.std_logic_arith.all;
6 use IEEE.std_logic_unsigned.all;
7 
8 entity udp_data_splicer is
9  port (
10  clk : in std_logic;
11  user_data : in std_logic_vector(7 downto 0);
12  gen_data : in std_logic_vector(7 downto 0);
13 
14  sel_user : in std_logic;
15 
16  udp_data_out : out std_logic_vector(7 downto 0)
17  ) ;
18 end;
19 
20 
21 architecture udp_data_splicer_arch of udp_data_splicer is
22 signal delay_sel_user : std_logic;
23 signal latched_user_data : std_logic_vector(7 downto 0);
24 begin
25 
26  udp_data_out <= gen_data when delay_sel_user = '0' else latched_user_data;
27  process(clk)
28  begin
29  if rising_edge(clk) then
30  latched_user_data <= user_data;
31  delay_sel_user <= sel_user;
32  end if;
33  end process;
34 
35 end udp_data_splicer_arch;