otsdaq_prepmodernization  v2_05_00
filter_data_out.vhd
1 -- Author: Ryan Rivera, FNAL
2 
3 library IEEE;
4 use IEEE.std_logic_1164.all;
5 use IEEE.std_logic_arith.all;
6 use IEEE.std_logic_unsigned.all;
7 
8  -- when enable is high out_data = rx_data, else out_data = 0.
9 entity filter_data_out is
10  port (
11  enable : in std_logic;
12 
13  clk : in std_logic;
14  us_clken : in std_logic;
15 
16  out_data_valid : out std_logic;
17 
18  rx_data : in std_logic_vector(7 downto 0);
19  out_data : out std_logic_vector(7 downto 0)
20  ) ;
21 end;
22 
23 
24 architecture filter_data_out_arch of filter_data_out is
25  signal d : std_logic_vector(7 downto 0);
26 begin
27 
28  d <= rx_data when enable = '1' else (others => '0');
29 
30  process(clk)
31  begin
32  if rising_edge(clk) then
33  if us_clken = '1' then
34  out_data <= d;
35  out_data_valid <= enable;
36  end if;
37  end if;
38  end process;
39 
40 end filter_data_out_arch;