 src | |
  firmware | |
   g-2 | |
    KickerControllerFirmware | |
     coregen | |
      fadc_mem_ste | |
       example_design | |
        bmg_wrapper.vhd | |
        fadc_mem_top.ucf | |
        fadc_mem_top.vhd | |
       implement | |
        planAhead_rdn.tcl | |
      fadc_mem.vhd | |
      fadc_mem_xmdf.tcl | |
     GEL_CAPTAN | |
      ipcore_dir | |
       ADC_FIFO | |
        example_design | |
         ADC_FIFO_exdes.ucf | |
         ADC_FIFO_exdes.vhd | |
        implement | |
         planAhead_ise.tcl | |
        simulation | |
         functional | |
          vcs_session.tcl | |
          wave_isim.tcl | |
         timing | |
          vcs_session.tcl | |
          wave_isim.tcl | |
         ADC_FIFO_dgen.vhd | |
         ADC_FIFO_dverif.vhd | |
         ADC_FIFO_pctrl.vhd | |
         ADC_FIFO_pkg.vhd | |
         ADC_FIFO_rng.vhd | |
         ADC_FIFO_synth.vhd | |
         ADC_FIFO_tb.vhd | |
       buf_one | |
        example_design | |
         buf_one_exdes.ucf | |
         buf_one_exdes.vhd | |
         buf_one_prod.vhd | |
        implement | |
         planAhead_ise.tcl | |
        simulation | |
         functional | |
          simcmds.tcl | |
          vcs_session.tcl | |
         timing | |
          simcmds.tcl | |
          vcs_session.tcl | |
         addr_gen.vhd | |
         bmg_stim_gen.vhd | |
         bmg_tb_pkg.vhd | |
         buf_one_synth.vhd | |
         buf_one_tb.vhd | |
         checker.vhd | |
         data_gen.vhd | |
         random.vhd | |
       ethernet_FIFO | |
        example_design | |
         ethernet_FIFO_exdes.ucf | |
         ethernet_FIFO_exdes.vhd | |
        implement | |
         planAhead_ise.tcl | |
        simulation | |
         functional | |
          vcs_session.tcl | |
          wave_isim.tcl | |
         timing | |
          vcs_session.tcl | |
          wave_isim.tcl | |
         ethernet_FIFO_dgen.vhd | |
         ethernet_FIFO_dverif.vhd | |
         ethernet_FIFO_pctrl.vhd | |
         ethernet_FIFO_pkg.vhd | |
         ethernet_FIFO_rng.vhd | |
         ethernet_FIFO_synth.vhd | |
         ethernet_FIFO_tb.vhd | |
       Ethernet_RAM | |
        example_design | |
         Ethernet_RAM_exdes.ucf | |
         Ethernet_RAM_exdes.vhd | |
         Ethernet_RAM_prod_exdes.vhd | |
        implement | |
         planAhead_ise.tcl | |
        simulation | |
         Ethernet_RAM_tb.vhd | |
         Ethernet_RAM_tb_agen.vhd | |
         Ethernet_RAM_tb_checker.vhd | |
         Ethernet_RAM_tb_dgen.vhd | |
         Ethernet_RAM_tb_pkg.vhd | |
         Ethernet_RAM_tb_rng.vhd | |
         Ethernet_RAM_tb_stim_gen.vhd | |
         Ethernet_RAM_tb_synth.vhd | |
       ethernetFIFO | |
        example_design | |
         ethernetFIFO_exdes.ucf | |
         ethernetFIFO_exdes.vhd | |
        implement | |
         planAhead_ise.tcl | |
        simulation | |
         functional | |
          isim | |
           ethernetFIFO_tb.exe.sim | |
            synopsys | |
             p_3308480207.c | |
            unisim | |
             a_1490675510_1976025627.c | |
             p_0947159679.c | |
            work | |
             a_0036521627_3367265570.c | |
             a_0066006188_3367265570.c | |
             a_0082216048_3367265570.c | |
             a_0086306375_3367265570.c | |
             a_0111163945_3367265570.c | |
             a_0123883550_3367265570.c | |
             a_0149863134_3367265570.c | |
             a_0153932009_3367265570.c | |
             a_0178783367_3367265570.c | |
             a_0191524528_3367265570.c | |
             a_0207865452_3367265570.c | |
             a_0228699227_3367265570.c | |
             a_0237336629_3367265570.c | |
             a_0242788730_3367265570.c | |
             a_0263897933_3367265570.c | |
             a_0266801666_3367265570.c | |
             a_0562365326_3192441503.c | |
             a_1416444588_3187800695.c | |
             a_1490552078_3468965345.c | |
             a_2290829330_1083906754.c | |
             a_2583630262_0912031422.c | |
             a_3114533131_1992432545.c | |
             a_3598191524_2126700906.c | |
             ethernetFIFO_tb.exe_main.c | |
             p_2318420936.c | |
            xilinxcorelib | |
             a_0209757386_3212880686.c | |
             a_1187796907_3212880686.c | |
             a_1995120943_3212880686.c | |
           precompiled.exe.sim | |
            ieee | |
             p_0017514958.c | |
             p_1242562249.c | |
             p_2592010699.c | |
             p_3499444699.c | |
             p_3564397177.c | |
             p_3620187407.c | |
            std | |
             textio.c | |
          vcs_session.tcl | |
          wave_isim.tcl | |
         timing | |
          vcs_session.tcl | |
          wave_isim.tcl | |
         ethernetFIFO_dgen.vhd | |
         ethernetFIFO_dverif.vhd | |
         ethernetFIFO_pctrl.vhd | |
         ethernetFIFO_pkg.vhd | |
         ethernetFIFO_rng.vhd | |
         ethernetFIFO_synth.vhd | |
         ethernetFIFO_tb.vhd | |
       EthernetRAM | |
        example_design | |
         EthernetRAM_exdes.ucf | |
         EthernetRAM_exdes.vhd | |
         EthernetRAM_prod.vhd | |
        implement | |
         planAhead_ise.tcl | |
        simulation | |
         functional | |
          simcmds.tcl | |
          vcs_session.tcl | |
         timing | |
          simcmds.tcl | |
          vcs_session.tcl | |
         addr_gen.vhd | |
         bmg_stim_gen.vhd | |
         bmg_tb_pkg.vhd | |
         checker.vhd | |
         data_gen.vhd | |
         EthernetRAM_synth.vhd | |
         EthernetRAM_tb.vhd | |
         random.vhd | |
       fifo_adc | |
        example_design | |
         fifo_adc_exdes.ucf | |
         fifo_adc_exdes.vhd | |
        implement | |
         planAhead_ise.tcl | |
        simulation | |
         functional | |
          vcs_session.tcl | |
          wave_isim.tcl | |
         timing | |
          vcs_session.tcl | |
          wave_isim.tcl | |
         fifo_adc_dgen.vhd | |
         fifo_adc_dverif.vhd | |
         fifo_adc_pctrl.vhd | |
         fifo_adc_pkg.vhd | |
         fifo_adc_rng.vhd | |
         fifo_adc_synth.vhd | |
         fifo_adc_tb.vhd | |
       ADC_FIFO.vhd | |
       ADC_FIFO_xmdf.tcl | |
       buf_one.vhd | |
       buf_one_xmdf.tcl | |
       create_ADC_FIFO.tcl | |
       create_ADCFiFo.tcl | |
       create_buf_one.tcl | |
       create_data.tcl | |
       create_data_shift.tcl | |
       create_ethernet_FIFO.tcl | |
       create_Ethernet_RAM.tcl | |
       create_ethernetBuffer.tcl | |
       create_ethernetFIFO.tcl | |
       create_EthernetRAM.tcl | |
       create_fifo_adc.tcl | |
       create_SandboxAdder.tcl | |
       edit_ADC_FIFO.tcl | |
       edit_buf_one.tcl | |
       edit_ethernet_FIFO.tcl | |
       edit_Ethernet_RAM.tcl | |
       edit_ethernetFIFO.tcl | |
       edit_EthernetRAM.tcl | |
       edit_fifo_adc.tcl | |
       ethernet_FIFO.vhd | |
       ethernet_FIFO_xmdf.tcl | |
       Ethernet_RAM.vhd | |
       Ethernet_RAM_xmdf.tcl | |
       ethernetFIFO.vhd | |
       ethernetFIFO_xmdf.tcl | |
       EthernetRAM.vhd | |
       EthernetRAM_xmdf.tcl | |
       fifo_adc.vhd | |
       fifo_adc_xmdf.tcl | |
       gen_ethernet_FIFO.tcl | |
      arp_reply.vhd | |
      blk_mem_gen_v2_6.vhd | |
      buffer_10bit.vhd | |
      buffer_12bit.vhd | |
      buffer_4x12_to_10.vhd | |
      buffer_60bit.vhd | |
      buffer_8bit.vhd | |
      burst_controller_sm.vhd | |
      burst_test_fifo64.vhd | |
      burst_throughput_test_blk.vhd | |
      burst_traffic_controller.vhd | |
      ClockLatchSignals.vhd | |
      ClockLatchSignals_tb.vhd | |
      CRC_splice.vhd | |
      create_packet.vhd | |
      DATA_FIFO_0.vhd | |
      data_send.vhd | |
      dataout_mux.vhd | |
      decipherer.vhd | |
      delay_counter.vhd | |
      dest_info_container.vhd | |
      dev_wr_gate.vhd | |
      dev_wr_gate_t.vhd | |
      DIG_GEC.vhd | |
      ethernetFIFOTester.vhd | |
      event_analysis.vhd | |
      ext_ip_addr_map.vhd | |
      fadc_mem.vhd | |
      fadc_params_package.vhd | |
      FADC_READ_CTRL.vhd | |
      FADC_WRITE_CTRL.vhd | |
      fake_user_data.vhd | |
      FIFO_SIM.vhd | |
      FIFO_SIM_tb.vhd | |
      filter_data_out.vhd | |
      GEC_RX_CTL_0.vhd | |
      GEC_RX_CTL_1.vhd | |
      GEC_RX_CTL_2.vhd | |
      GEC_RX_CTL_8.vhd | |
      GEC_RX_DATA_MUX.vhd | |
      GEC_TX_CTL_0.vhd | |
      GEC_TX_CTL_1.vhd | |
      GEC_TX_CTL_8.vhd | |
      GEC_TX_SEQ_CTL_8.vhd | |
      IDELAY_CTRL.vhd | |
      INFO_FIFO64_0.vhd | |
      INFO_FIFO_0.vhd | |
      ip_checksum_calc.vhd | |
      MUX16_2.vhd | |
      MUX64_2.vhd | |
      MUX64_4.vhd | |
      MUX64_8.vhd | |
      or33.vhd | |
      pa.fromNcd.tcl | |
      params_package.vhd | |
      PeakFinder.vhd | |
      PeakFinder_tb.vhd | |
      psudo_data_allOne.vhd | |
      PsudoCounter.vhd | |
      psudoData.vhd | |
      Pulser.vhd | |
      RAM_COMM_DEC_9.vhd | |
      RX_IN_LATCH.vhd | |
      Sample_Manager.vhd | |
      stat_mux.vhd | |
      stat_pulse.vhd | |
      TOP_LEVEL.ucf | |
      TOP_LEVEL.vhd | |
      TOP_LEVEL_old.ucf | |
      trigger_recv_blk.vhd | |
      udp_data_splicer.vhd | |
      user_addrs_mux.vhd | |
      VERSION_BLK.vhd | |
     ipcore_dir | |
      ADDR_FIFO | |
       example_design | |
        ADDR_FIFO_exdes.ucf | |
        ADDR_FIFO_exdes.vhd | |
       implement | |
        planAhead_ise.tcl | |
       simulation | |
        functional | |
         vcs_session.tcl | |
         wave_isim.tcl | |
        timing | |
         vcs_session.tcl | |
         wave_isim.tcl | |
        ADDR_FIFO_dgen.vhd | |
        ADDR_FIFO_dverif.vhd | |
        ADDR_FIFO_pctrl.vhd | |
        ADDR_FIFO_pkg.vhd | |
        ADDR_FIFO_rng.vhd | |
        ADDR_FIFO_synth.vhd | |
        ADDR_FIFO_tb.vhd | |
      DATA_FIFO_0 | |
       example_design | |
        DATA_FIFO_0_exdes.ucf | |
        DATA_FIFO_0_exdes.vhd | |
       implement | |
        planAhead_ise.tcl | |
       simulation | |
        functional | |
         vcs_session.tcl | |
         wave_isim.tcl | |
        timing | |
         vcs_session.tcl | |
         wave_isim.tcl | |
        DATA_FIFO_0_dgen.vhd | |
        DATA_FIFO_0_dverif.vhd | |
        DATA_FIFO_0_pctrl.vhd | |
        DATA_FIFO_0_pkg.vhd | |
        DATA_FIFO_0_rng.vhd | |
        DATA_FIFO_0_synth.vhd | |
        DATA_FIFO_0_tb.vhd | |
      INFO_FIFO_0 | |
       example_design | |
        INFO_FIFO_0_exdes.ucf | |
        INFO_FIFO_0_exdes.vhd | |
       implement | |
        planAhead_ise.tcl | |
       simulation | |
        functional | |
         vcs_session.tcl | |
         wave_isim.tcl | |
        timing | |
         vcs_session.tcl | |
         wave_isim.tcl | |
        INFO_FIFO_0_dgen.vhd | |
        INFO_FIFO_0_dverif.vhd | |
        INFO_FIFO_0_pctrl.vhd | |
        INFO_FIFO_0_pkg.vhd | |
        INFO_FIFO_0_rng.vhd | |
        INFO_FIFO_0_synth.vhd | |
        INFO_FIFO_0_tb.vhd | |
      ADDR_FIFO.vhd | |
      ADDR_FIFO_xmdf.tcl | |
      DATA_FIFO_0.vhd | |
      DATA_FIFO_0_xmdf.tcl | |
      INFO_FIFO_0.vhd | |
      INFO_FIFO_0_xmdf.tcl | |
     oei | |
      address_container.vhd | |
      arp_reply.vhd | |
      burst_controller_sm.vhd | |
      burst_traffic_controller.vhd | |
      clock_constraints.ucf | |
      crc_splice.vhd | |
      create_packet.vhd | |
      data_manager.vhd | |
      dataout_mux.vhd | |
      decipherer.vhd | |
      ethernet_controller.vhd | |
      ethernet_controller_wrapper.vhd | |
      ethernet_interface.vhd | |
      filter_data_out.vhd | |
      icmp_ping_checksum_calc.vhd | |
      icmp_ping_shift_reg.vhd | |
      ip_checksum_calc.vhd | |
      or33.vhd | |
      params_package.vhd | |
      pins.ucf | |
      ram_comm_dec.vhd | |
      reset_mgr.vhd | |
      rx_ctl.vhd | |
      TOP_LEVEL.vhd | |
      tx_seq_ctl.vhd | |
      udp_data_splicer.vhd | |
      user_addrs_mux.vhd | |
      xmii_handler.vhd | |
     Python Scripts | |
      readDataExample.py | |
  otsdaq-prepmodernization | |
   DataProcessorPlugins | |
    BurstDataAndTimeSaverConsumer.h | |
    BurstDataAndTimeSaverConsumer_processor.cc | |
    NimStreamConsumer.h | |
    NimStreamConsumer_processor.cc | |
   FEInterfaces | |
    FENIMPlusInterface.h | |
    FENIMPlusInterface_interface.cc | |
  UserWebGUI | |
   js | |
    CanvasLineChart.js | |
    jquery.mask.min.js | |
    jscolor.min.js | |
    NimPlus_app.js | |
    NimStream_app.js | |