otsdaq_prepmodernization  v2_05_00
GEC_RX_CTL_8.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : GEC_RX_CTL_8
4 -- Design : ethernet_controller
5 -- Author : aprosser
6 -- Company : CD_CEPA_ESE
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : c:\HDL_Designs\dig_gec\ethernet_controller\compile\GEC_RX_CTL_8.vhd
11 -- Generated : 03/20/09 15:19:32
12 -- From : c:/HDL_Designs/dig_gec/ethernet_controller/src/GEC_RX_CTL_8.asf
13 -- By : FSM2VHDL ver. 5.0.5.6
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_arith.all;
24 use IEEE.std_logic_unsigned.all;
25 use params_package.all;
26 
27 entity GEC_RX_CTL_8 is
28  port (
29  block_en: in STD_LOGIC;
30  clock: in STD_LOGIC;
31  data_fifo_full: in STD_LOGIC;
32  data_fifo_wrerr: in STD_LOGIC;
33  gec_user_crc_err: in STD_LOGIC;
34  gec_user_rx_data_out: in STD_LOGIC_VECTOR (7 downto 0);
35  gec_user_rx_size_out: in STD_LOGIC_VECTOR (10 downto 0);
36  gec_user_rx_valid_out: in STD_LOGIC;
37  reset_n: in STD_LOGIC;
38  crc_err_flag: out STD_LOGIC;
39  data_fifo_q_w_data: out STD_LOGIC_VECTOR (63 downto 0);
40  data_fifo_wren: out STD_LOGIC;
41  info_fifo_wr_data: out STD_LOGIC_VECTOR (15 downto 0);
42  info_fifo_wren: out STD_LOGIC);
43 end GEC_RX_CTL_8;
44 
45 architecture GEC_RX_CTL_8 of GEC_RX_CTL_8 is
46 
47 -- diagram signals declarations
48 signal com_code: STD_LOGIC_VECTOR (2 downto 0);
49 signal crc_err_reg: STD_LOGIC;
50 signal crc_loop_count: STD_LOGIC_VECTOR (4 downto 0);
51 signal q_w_count: STD_LOGIC_VECTOR (7 downto 0);
52 signal q_w_counter: STD_LOGIC_VECTOR (7 downto 0);
53 signal q_w_reg: STD_LOGIC_VECTOR (63 downto 0);
54 
55 -- BINARY ENCODED state machine: Sreg0
56 attribute enum_encoding: string;
57 type Sreg0_type is (
58  idle, enabled, rcvdone, S1, check_crc, S2, S3_S4, S3_S7, S3_S8, S3_S9, S3_S10, S3_S11, S3_S12, S3_S6, S3_S5, S13
59 );
60 attribute enum_encoding of Sreg0_type: type is
61  "0000 " & -- idle
62  "0001 " & -- enabled
63  "0010 " & -- rcvdone
64  "0011 " & -- S1
65  "0100 " & -- check_crc
66  "0101 " & -- S2
67  "0110 " & -- S3_S4
68  "0111 " & -- S3_S7
69  "1000 " & -- S3_S8
70  "1001 " & -- S3_S9
71  "1010 " & -- S3_S10
72  "1011 " & -- S3_S11
73  "1100 " & -- S3_S12
74  "1101 " & -- S3_S6
75  "1110 " & -- S3_S5
76  "1111" ; -- S13
77 
78 signal Sreg0: Sreg0_type;
79 
80 attribute state_vector: string;
81 attribute state_vector of GEC_RX_CTL_8: architecture is "Sreg0";
82 
83 begin
84 
85 
86 ----------------------------------------------------------------------
87 -- Machine: Sreg0
88 ----------------------------------------------------------------------
89 Sreg0_machine: process (clock)
90 begin
91  if clock'event and clock = '1' then
92  if reset_n = '0' then
93  Sreg0 <= idle;
94  -- Set default values for outputs, signals and variables
95  -- ...
96  crc_err_reg <= '0';
97  crc_loop_count <= v_5_0;
98  q_w_reg <= v_32_0 & v_32_0;
99 -- Initialize error flag outputs
100  crc_err_flag <= '0';
101 -- Initialize FIFO control outputs
102  data_fifo_wren <= '0';
103  info_fifo_wren <= '0';
104  info_fifo_wr_data <= v_16_0;
105  com_code <= "000";
106  data_fifo_q_w_data <= (others => '0');
107  else
108  -- Set default values for outputs, signals and variables
109  -- ...
110  case Sreg0 is
111  when idle =>
112  if block_en = '0' then
113  Sreg0 <= idle;
114  elsif block_en = '1' then
115  Sreg0 <= enabled;
116  end if;
117  when enabled =>
118  if gec_user_rx_valid_out = '1' and
119  block_en = '1' and
120  gec_user_rx_size_out > v_11_1 then
121  Sreg0 <= S13;
122  info_fifo_wr_data(7 downto 0) <= gec_user_rx_data_out;
123  -- Put the entire command/size word in the info
124  -- FIFO
125  -- this is not written until
126  -- all info for the fifo is
127  -- accumulated
128  --q_w_count <= gec_user_rx_data_out (7 downto 3);
129  -- set the terminal count of quad words
130  -- using that portion of the command/size
131  -- word
132  com_code <= gec_user_rx_data_out(2 downto 0);
133  -- save command code
134  elsif gec_user_rx_valid_out = '0' and
135  block_en = '1' then
136  Sreg0 <= enabled;
137  elsif block_en = '0' then
138  Sreg0 <= idle;
139  elsif gec_user_rx_valid_out = '1' and
140  block_en = '1' and
141  gec_user_rx_size_out = v_11_1 then
142  Sreg0 <= check_crc;
143  info_fifo_wr_data(7 downto 0) <= gec_user_rx_data_out;
144  info_fifo_wr_data(15 downto 8) <= v_8_0;
145  -- Capture command byte
146  end if;
147  when rcvdone =>
148  if block_en = '0' then
149  Sreg0 <= idle;
150  info_fifo_wren <= '0';
151  elsif block_en = '1' then
152  Sreg0 <= enabled;
153  info_fifo_wren <= '0';
154  end if;
155  when S1 =>
156  Sreg0 <= S2;
157  info_fifo_wr_data(3) <= crc_err_reg;
158  -- keep the crc error status
159  -- at this point the info should be complete
160  crc_err_flag <= crc_err_reg;
161  -- assert the crc error status on the output
162  when check_crc =>
163  if (crc_loop_count = v_5_22) or
164  (gec_user_crc_err = '1') or
165  (crc_err_reg = '1') then -- CRC timed out -- or CRC err detected
166  Sreg0 <= S1;
167  if (gec_user_crc_err = '1') then
168  crc_err_reg <= '1';
169  end if;
170  elsif (crc_loop_count < v_5_22) and
171  (gec_user_crc_err = '0') then -- waiting for CRC time out
172  Sreg0 <= check_crc;
173  crc_loop_count <= crc_loop_count + v_5_1;
174  end if;
175  when S2 =>
176  Sreg0 <= rcvdone;
177  crc_err_reg <= '0';
178  -- reset the crc error counter
179  crc_err_flag <= '0';
180  -- reset the crc error flag (output)
181  crc_loop_count <= v_5_0;
182  -- reset the 22 cycle crc loop counter
183  data_fifo_wren <= '0';
184  info_fifo_wren <= '1';
185  -- we actually write the info fifo here.
186  when S13 =>
187  Sreg0 <= S3_S4;
188  q_w_count <= gec_user_rx_data_out;
189  info_fifo_wr_data(15 downto 8) <= gec_user_rx_data_out;
190  when S3_S4 =>
191  Sreg0 <= S3_S5;
192  data_fifo_q_w_data(63 downto 56) <= gec_user_rx_data_out;
193  q_w_counter <= v_8_1;
194  -- initialize the counter
195  case com_code is
196  when "000" =>
197  -- read
198  q_w_count <= v_8_1;
199  -- Increment the quad word count for writes
200  -- First word is the starting address
201  -- next n words (I received a count of n)
202  -- is the actual quad word data for writing.
203  -- This will cause only the address word
204  -- to be written to the data fifo.
205  when "001" =>
206  -- write
207  q_w_count <= q_w_count + v_8_1;
208  -- watch out for overflow
209  -- writes the starting address first plus the
210  -- data
211  when "010" =>
212  -- read
213  q_w_count <= v_8_1;
214  -- This will cause only the address word
215  -- to be written to the data fifo.
216  when "011" =>
217  -- read
218  q_w_count <= v_8_1;
219  -- This will cause only the address word
220  -- to be written to the data fifo.
221  when others =>
222  q_w_count <= v_8_1;
223  end case;
224  when S3_S7 =>
225  Sreg0 <= S3_S8;
226  data_fifo_q_w_data(39 downto 32) <= gec_user_rx_data_out;
227  when S3_S8 =>
228  Sreg0 <= S3_S9;
229  data_fifo_q_w_data(31 downto 24) <= gec_user_rx_data_out;
230  when S3_S9 =>
231  Sreg0 <= S3_S10;
232  data_fifo_q_w_data(23 downto 16) <= gec_user_rx_data_out;
233  when S3_S10 =>
234  Sreg0 <= S3_S11;
235  data_fifo_q_w_data(15 downto 8) <= gec_user_rx_data_out;
236  when S3_S11 =>
237  Sreg0 <= S3_S12;
238  data_fifo_wren <= '1';
239  -- write the assembled data to the FIFO
240  data_fifo_q_w_data(7 downto 0) <= gec_user_rx_data_out;
241  when S3_S12 =>
242  if q_w_counter < q_w_count then
243  Sreg0 <= S3_S5;
244  data_fifo_q_w_data(63 downto 56) <= gec_user_rx_data_out;
245  data_fifo_wren <= '0';
246  -- Finish the write to the data fifo
247  q_w_counter <= q_w_counter + v_8_1;
248  -- increment the counter
249  elsif q_w_counter = q_w_count then
250  Sreg0 <= check_crc;
251  data_fifo_wren <= '0';
252  -- finish data FIFO write
253  if (gec_user_crc_err = '1') then
254  crc_err_reg <= '1';
255  end if;
256  crc_loop_count <= crc_loop_count + v_5_1;
257  -- increment loop counter for catching CRC errors
258  end if;
259  when S3_S6 =>
260  Sreg0 <= S3_S7;
261  data_fifo_q_w_data(47 downto 40) <= gec_user_rx_data_out;
262  when S3_S5 =>
263  Sreg0 <= S3_S6;
264  data_fifo_q_w_data(55 downto 48) <= gec_user_rx_data_out;
265 --vhdl_cover_off
266  when others =>
267  null;
268 --vhdl_cover_on
269  end case;
270  end if;
271  end if;
272 end process;
273 
274 end GEC_RX_CTL_8;