otsdaq_prepmodernization  v2_05_00
FADC_WRITE_CTRL.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer: Ryan Rivera, rrivera@fnal.gov
4 --
5 -- Create Date: 11:09:15 07/28/2011
6 -- Design Name:
7 -- Module Name: FADC_WRITE_CTRL - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.std_logic_1164.all;
22 use IEEE.std_logic_arith.all;
23 use IEEE.std_logic_unsigned.all;
24 use fadc_params_package.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 --library UNISIM;
33 --use UNISIM.VComponents.all;
34 
35 entity FADC_WRITE_CTRL is
36  Port ( fadc_dclk : in STD_LOGIC;
37  reset : in STD_LOGIC;
38  trigger : in STD_LOGIC;
39  rdy_for_trig : in STD_LOGIC; --from readout controller
40  post_trig_count : in STD_LOGIC_VECTOR (MEM_ADDR_SIZE-1 downto 0); -- num of samples to take after trigger
41  we_rise : out STD_LOGIC;
42  waddr_rise : out STD_LOGIC_VECTOR (MEM_ADDR_SIZE-1 downto 0);
43  dout_dbg_rise : out STD_LOGIC_VECTOR (31 downto 0);
44  dout_dbg_fall : out STD_LOGIC_VECTOR (31 downto 0);
45  we_fall : out STD_LOGIC;
46  waddr_fall : out STD_LOGIC_VECTOR (MEM_ADDR_SIZE-1 downto 0);
47  done : out STD_LOGIC); -- rising edge of done indicates ready to read
48 end FADC_WRITE_CTRL;
49 
50 
51 architecture Behavioral of FADC_WRITE_CTRL is
52 
53  signal cnt: integer range 0 to 2**MEM_ADDR_SIZE-1; --count number of samples after trigger
54  signal trigger_old: STD_LOGIC;
55  signal rdy_for_trig_old: STD_LOGIC;
56  signal actually_ready: STD_LOGIC;
57  signal done_sig: STD_LOGIC;
58  signal we_rise_sig: STD_LOGIC;
59  signal halt: STD_LOGIC;
60  signal waddr_rise_sig: STD_LOGIC_VECTOR (MEM_ADDR_SIZE-1 downto 0);
61  signal waddr_fall_sig: STD_LOGIC_VECTOR (MEM_ADDR_SIZE-1 downto 0);
62 
63 begin
64 
65 --desc:
66  --on rising edge
67  --we_rise=0.
68  --if reset, waddr_rise=0, done=1.
69  --if rdy_for_trig and done and trigger rising edge, cnt = 0, done=0.
70  --if rising rdy_for_trig, halt=0.
71  --if cnt = post_trig_count and done=0, done=1, halt = 1; else if halt=0 we_rise = 1,waddr_rise++. --reason why 0 is invalid
72  --if done=0, cnt++.
73  --on falling edge
74  --during reset, we_fall=0, waddr_fall=0.
75  --if we_rise = 1, we_fall = 1, waddr_fall++; else we_fall = 0.
76 
77  done <= halt;
78  we_rise <= we_rise_sig;
79  waddr_rise <= waddr_rise_sig;
80  waddr_fall <= waddr_fall_sig;
81 
82  dout_dbg_rise <= x"1" & "00" & waddr_rise_sig & x"0" & "00" & waddr_rise_sig;
83  dout_dbg_fall <= x"3" & "00" & waddr_fall_sig & x"2" & "00" & waddr_fall_sig;
84 
85  process(fadc_dclk)
86  begin
87 
88  ------------------------------------
89  --================================-- RISING EDGE PROCESS
90  ------------------------------------
91  if rising_edge(fadc_dclk) then
92 
93  we_rise_sig <= '0';
94  trigger_old <= trigger;
95  rdy_for_trig_old <= rdy_for_trig;
96 
97  if reset = '1' then
98  waddr_rise_sig <= (others => '0');
99  done_sig <= '1'; --done is 0 while counting after trigger
100  halt <= '0'; --halt is 1 once counting has stopped
101  actually_ready <= '0';
102  cnt <= 0;
103  else
104 
105  if actually_ready = '1' and trigger_old = '0' and trigger = '1' then
106  cnt <= 0;
107  actually_ready <= '0';
108  done_sig <= '0';
109  end if;
110 
111  if rdy_for_trig_old = '0' and rdy_for_trig = '1' and halt = '1' then --come out of done
112  halt <= '0'; --continuously take data
113  end if;
114 
115  if actually_ready = '0' and halt = '0' and done_sig = '1' then --wait while buffer fills up before taking data again
116 
117  if cnt = 2**MEM_ADDR_SIZE-1 then
118  actually_ready <= '1'; --continuously take data
119  else
120  cnt <= cnt + 1;
121  end if;
122 
123  end if;
124 
125  -- above is coming out of last read and receiving next trigger
126  ---------------
127  -- below is the read process
128 
129  if conv_std_logic_vector(cnt,10) = post_trig_count and done_sig = '0' then
130  done_sig <= '1';
131  halt <= '1';
132  cnt <= 0;
133  else
134  if halt = '0' then
135  we_rise_sig <= '1';
136  waddr_rise_sig <= waddr_rise_sig + 1;
137  end if;
138 
139  if done_sig = '0' then
140  if cnt = 2**MEM_ADDR_SIZE-1 then
141  cnt <= 0;
142  else
143  cnt <= cnt + 1;
144  end if;
145  end if;
146  end if;
147 
148  end if;
149 
150  end if;
151 
152 
153  ------------------------------------
154  --================================-- FALLING EDGE PROCESS
155  ------------------------------------
156 
157  if falling_edge(fadc_dclk) then
158 
159  we_fall <= '0';
160 
161  if reset = '1' then
162  waddr_fall_sig <= (others => '0');
163  elsif we_rise_sig = '1' then
164  we_fall <= '1';
165  waddr_fall_sig <= waddr_fall_sig + 1;
166  end if;
167 
168  end if;
169 
170  end process;
171 
172 
173 end Behavioral;