4 #include "otsdaq/Macros/CoutMacros.h"
5 #include "otsdaq/Macros/InterfacePluginMacros.h"
6 #include "otsdaq/MessageFacility/MessageFacility.h"
7 #include "otsdaq-prepmodernization/FEInterfaces/FENIMPlusInterface.h"
12 #define __MF_SUBJECT__ "FE-FENIMPlusInterface"
14 FENIMPlusInterface::FENIMPlusInterface(
const std::string& interfaceUID,
15 const ConfigurationTree& theXDAQContextConfigTree,
16 const std::string& interfaceConfigurationPath)
17 : Socket(theXDAQContextConfigTree.getNode(interfaceConfigurationPath)
18 .getNode(
"HostIPAddress")
19 .getValue<std::string>(),
20 theXDAQContextConfigTree.getNode(interfaceConfigurationPath)
22 .getValue<unsigned int>())
23 , FEOtsUDPTemplateInterface(
24 interfaceUID, theXDAQContextConfigTree, interfaceConfigurationPath)
27 registerFEMacroFunction(
29 static_cast<FEVInterface::frontEndMacroFunction_t>(
30 &FENIMPlusInterface::FEMacroGenerateTriggers),
31 std::vector<std::string>{
"numberOfTriggers",
34 std::vector<std::string>{
"triggersWereLaunched"},
40 FENIMPlusInterface::~FENIMPlusInterface(
void) {}
43 void FENIMPlusInterface::configure(
void)
45 __CFG_COUT__ <<
"configure" << std::endl;
47 ConfigurationTree optionalLink =
48 theXDAQContextConfigTree_.getNode(theConfigurationPath_)
49 .getNode(
"LinkToOptionalParameters");
50 bool usingOptionalParams = !optionalLink.isDisconnected();
52 std::string writeBuffer;
53 std::string readBuffer;
54 uint64_t readQuadWord;
56 addrOffset = optionalLink.getNode(
"AddressOffset").getValue<uint64_t>();
57 __CFG_COUT__ <<
"FW Block Address offset is configured as: 0x" << std::hex << addrOffset << __E__;
67 if((usingOptionalParams &&
68 optionalLink.getNode(
"EnableClockResetDuringConfigure").getValue<
bool>() &&
69 optionalLink.getNode(
"PrimaryBoardConfig").getValue<
bool>()))
71 __CFG_COUT__ <<
"\"Soft\" Resetting NIM PLUS Ethernet!" << std::endl;
73 OtsUDPFirmwareCore::softEthernetReset(writeBuffer);
74 OtsUDPHardware::write(writeBuffer);
75 OtsUDPFirmwareCore::clearEthernetReset(writeBuffer);
76 OtsUDPHardware::write(writeBuffer);
82 __CFG_COUT__ <<
"Could not find reset clock flag, so not resetting... "
86 FEOtsUDPTemplateInterface::configure();
87 if((optionalLink.getNode(
"PrimaryBoardConfig").getValue<
bool>())){
90 uint64_t iomux_config = 0x0;
91 uint64_t input_mux_config = ((optionalLink.getNode(
"InputMuxConfig").getValue<uint32_t>()));
92 uint64_t output_mux_config = ((optionalLink.getNode(
"OutputMuxConfig").getValue<uint32_t>())) ;
95 iomux_config = (output_mux_config << 32) | input_mux_config;
96 __CFG_COUT__ <<
"input mux config : 0x" << std::hex << input_mux_config << std::hex << __E__;
97 __CFG_COUT__ <<
"output mux config : 0x" << std::hex << output_mux_config << __E__;
98 __CFG_COUT__ <<
"output mux config shifted: 0x" << std::hex << (output_mux_config << 32) << __E__;
99 __CFG_COUT__ <<
"iomux config : 0x" << std::hex << iomux_config << __E__;
101 OtsUDPFirmwareCore::writeAdvanced(
102 writeBuffer, 0x10000000999, iomux_config);
103 OtsUDPHardware::write(writeBuffer);
108 __CFG_COUT__ <<
"Choosing external or internal clock..." << std::endl;
109 OtsUDPFirmwareCore::writeAdvanced(
113 ? (optionalLink.getNode(
"UseExternalClock").getValue<
bool>() ? 1 : 0)
115 (((usingOptionalParams
116 ? (optionalLink.getNode(
"ExternalClockSource").getValue<unsigned int>()
117 ? (optionalLink.getNode(
"ExternalClockSource")
118 .getValue<unsigned int>() -
130 ? (optionalLink.getNode(
"UseExternalClock").getValue<
bool>() ? 1 : 0)
132 (((usingOptionalParams
133 ? (optionalLink.getNode(
"ExternalClockSource").getValue<unsigned int>()
134 ? (optionalLink.getNode(
"ExternalClockSource")
135 .getValue<unsigned int>() -
142 __CFG_COUT__ <<
"CHOOSING EXTERNAL CLOCK: " << usingOptionalParams <<
" : "
143 << optionalLink.getNode(
"UseExternalClock").getValue<
bool>() <<
" : "
144 << optionalLink.getNode(
"ExternalClockSource").getValue<
unsigned int>()
145 << std::hex <<
" : " << val << std::dec << std::endl;
147 OtsUDPHardware::write(writeBuffer);
150 OtsUDPFirmwareCore::readAdvanced(writeBuffer,
152 OtsUDPHardware::read(writeBuffer,
156 OtsUDPFirmwareCore::readAdvanced(writeBuffer, addrOffset + 0x10);
157 OtsUDPHardware::read(writeBuffer, readQuadWord);
158 __CFG_COUT__ <<
"Clocks lock loss " << ((readQuadWord >> 24) & 0xF) << __E__;
162 if(!((readQuadWord >> 24) & 0xF))
164 __CFG_COUT__ <<
"Re-locking clocks..." << std::endl;
166 OtsUDPFirmwareCore::writeAdvanced(
167 writeBuffer, 0x999, 0x7);
168 OtsUDPHardware::write(writeBuffer);
170 OtsUDPFirmwareCore::writeAdvanced(
171 writeBuffer, 0x999, 0);
172 OtsUDPHardware::write(writeBuffer);
174 OtsUDPFirmwareCore::writeAdvanced(
175 writeBuffer, 0x999, 0x8);
176 OtsUDPHardware::write(writeBuffer);
178 OtsUDPFirmwareCore::writeAdvanced(
179 writeBuffer, 0x999, 0);
180 OtsUDPHardware::write(writeBuffer);
184 OtsUDPFirmwareCore::readAdvanced(writeBuffer, addrOffset + 0x10);
185 OtsUDPHardware::read(writeBuffer, readQuadWord);
186 __CFG_COUT__ <<
"Clocks lock loss " << ((readQuadWord >> 24) & 0xF) << __E__;
190 OtsUDPFirmwareCore::readAdvanced(writeBuffer,addrOffset + 0x5);
191 OtsUDPHardware::read(writeBuffer,readBuffer);
204 OtsUDPFirmwareCore::writeAdvanced(
205 writeBuffer, addrOffset + 0x4, 0x3);
206 OtsUDPHardware::write(writeBuffer);
208 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x18016, 0x3);
209 OtsUDPHardware::write(writeBuffer);
211 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x18017, 0x3);
212 OtsUDPHardware::write(writeBuffer);
214 OtsUDPFirmwareCore::writeAdvanced(
215 writeBuffer, addrOffset + 0x5, 0x0);
216 OtsUDPHardware::write(writeBuffer);
218 OtsUDPFirmwareCore::writeAdvanced(
219 writeBuffer, addrOffset + 0x18013, 0x0);
220 OtsUDPHardware::write(writeBuffer);
222 OtsUDPFirmwareCore::writeAdvanced(
223 writeBuffer, addrOffset + 0x18014, 0x0);
224 OtsUDPHardware::write(writeBuffer);
226 OtsUDPFirmwareCore::writeAdvanced(
227 writeBuffer, addrOffset + 0x18015, 0x0);
228 OtsUDPHardware::write(writeBuffer);
230 OtsUDPFirmwareCore::writeAdvanced(
231 writeBuffer, addrOffset + 0x1800C, 0xF);
232 OtsUDPHardware::write(writeBuffer);
234 sel_ctl_register_ = 0x0;
235 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x6, sel_ctl_register_);
236 OtsUDPHardware::write(writeBuffer);
239 __CFG_COUT__ <<
"Initializing counter/sig-gen/acc-sync resets and enables." << __E__;
246 OtsUDPFirmwareCore::writeAdvanced(writeBuffer,addrOffset + 0x18000,nimResets_.to_ulong());
247 OtsUDPHardware::write(writeBuffer);
248 OtsUDPFirmwareCore::writeAdvanced(writeBuffer,addrOffset + 0x18001,nimEnables_.to_ulong());
249 OtsUDPHardware::write(writeBuffer);
253 OtsUDPFirmwareCore::writeAdvanced(
254 writeBuffer, addrOffset + 0x18000, nimResets_.to_ulong());
255 OtsUDPHardware::write(writeBuffer);
257 std::array<std::string, 4> v1channelNames(
258 {
"ChannelA",
"ChannelB",
"ChannelC",
"ChannelD"});
259 std::array<std::string, 8> v2channelNames(
260 {
"ChannelA",
"ChannelB",
"ChannelC",
"ChannelD",
"ChannelE",
"ChannelF",
"ChannelG",
"ChannelH"});
263 bool doWriteDACs =
false;
267 usingOptionalParams &&
268 optionalLink.getNode(
"EnableDACSetupDuringConfigure").getValue<
bool>() &&
269 optionalLink.getNode(
"PrimaryBoardConfig").getValue<
bool>();
274 __CFG_COUT__ <<
"Skipping DAC writing because enable field was not found in tree."
280 __CFG_COUT__ <<
"Setting up DACs" << std::endl;
281 const std::string dacValueField =
"DACValue";
282 if(optionalLink.getNode(
"BoardVersion").getValue<
int>() == 1){
284 for(
const auto& channelName : v1channelNames){
285 changeDACLevelv1(channelName,
286 optionalLink.getNode(dacValueField + channelName)
287 .getValue<
unsigned short>());
290 else if (optionalLink.getNode(
"BoardVersion").getValue<
int>() == 2){
292 for(
const auto& channelName : v2channelNames){
293 changeDACLevelv2(channelName,
294 optionalLink.getNode(dacValueField + channelName)
295 .getValue<
unsigned short>());
299 __CFG_COUT_ERR__ <<
"Error! No DAC's Set! Invalid NIM+ Board version was specified during DAC Setup! Make sure you've set a valid version (1 or 2)" << std::endl;
307 unsigned char channelCount = 0;
311 unsigned int logicInput;
312 uint64_t inputModMask;
313 unsigned int inputDelay;
314 unsigned int inputWidth;
316 unsigned char inputPolarityMask = 0;
318 __CFG_COUT__ <<
"Setting up input channels..." << std::endl;
319 for(
const auto& channelName : v1channelNames)
328 logicInput = theXDAQContextConfigTree_.getNode(theConfigurationPath_)
329 .getNode(
"LogicInput" + channelName)
330 .getValue<
unsigned int>();
333 sel_ctl_register_ |= (logicInput & 0x3) << (channelCount * 2 + 8);
334 __CFG_COUT__ <<
"Logic input " << channelName <<
" : " << logicInput
335 <<
" => sel_ctl_register_= " << std::hex << sel_ctl_register_
336 << std::dec << std::endl;
337 if(usingOptionalParams)
339 inputDelay = optionalLink.getNode(
"DelayInput" + channelName)
340 .getValue<
unsigned int>();
341 inputWidth = optionalLink.getNode(
"WidthInput" + channelName)
342 .getValue<
unsigned int>();
343 inputModMask = (0xFFFFFFFFFFFFFFFF >> (64 - inputWidth)) << inputDelay;
357 invertPolarity = usingOptionalParams &&
358 optionalLink.getNode(
"InvertPolarityInput" + channelName)
361 inputPolarityMask |= ((invertPolarity ? 1 : 0) << channelCount);
363 __CFG_COUT__ <<
"Output word for " << channelName <<
" is "
364 << std::bitset<64>(inputModMask) << std::endl
365 <<
" with a delay of " << inputDelay <<
" and a width of "
366 << inputWidth << std::endl;
368 OtsUDPFirmwareCore::writeAdvanced(writeBuffer,
369 addrOffset + ((channelCount + 1) << 8),
371 OtsUDPHardware::write(writeBuffer);
373 OtsUDPFirmwareCore::writeAdvanced(
375 addrOffset + (((channelCount + 1) << 8) | 0x2),
377 OtsUDPHardware::write(writeBuffer);
385 __CFG_COUT__ <<
"Input polarity mask is " << std::bitset<8>(inputPolarityMask)
387 OtsUDPFirmwareCore::writeAdvanced(
389 addrOffset + 0x1800B,
391 OtsUDPHardware::write(writeBuffer);
394 __CFG_COUT__ <<
" sel_ctl_register_: " << std::bitset<16>(sel_ctl_register_)
396 OtsUDPFirmwareCore::writeAdvanced(
402 OtsUDPHardware::write(writeBuffer);
404 __CFG_COUT__ <<
"Writing 40 MHz clock delay." << __E__;
405 OtsUDPFirmwareCore::writeAdvanced(
409 ? optionalLink.getNode(
"40MHzClockDelay").getValue<
unsigned int>()
412 OtsUDPHardware::write(writeBuffer);
414 __CFG_COUT__ <<
"Writing clock mask setup." << __E__;
415 OtsUDPFirmwareCore::writeAdvanced(
417 addrOffset + 0x18008,
420 ? optionalLink.getNode(
"ClockMaskSetup").getValue<
unsigned int>()
422 OtsUDPHardware::write(writeBuffer);
426 OtsUDPFirmwareCore::writeAdvanced(
428 addrOffset + 0x18000,
429 nimResets_.to_ulong());
430 OtsUDPHardware::write(writeBuffer);
433 OtsUDPFirmwareCore::writeAdvanced(
435 addrOffset + 0x18000,
436 nimResets_.to_ulong());
437 OtsUDPHardware::write(writeBuffer);
439 __CFG_COUT__ <<
"Clock mask setup: " << std::hex
440 << optionalLink.getNode(
"ClockMaskSetup").getValue<
unsigned int>()
441 << std::dec << std::endl;
443 catch(
const std::runtime_error& e)
445 __CFG_COUT__ <<
"Failed input stage setup!\n" << e.what() << std::endl;
452 unsigned char channelCount = 0;
454 unsigned int outputDelay;
455 unsigned int outputWidthMask;
456 uint64_t outputWidth;
457 uint64_t outputModMask;
459 unsigned int outputMuxSelect;
460 unsigned int outputChannelSourceSelect;
461 unsigned int outputTimeVetoDuration, outputPrescaleCount;
462 bool outputBackpressureSelect;
463 unsigned char backpressureMask = 0;
464 unsigned int gateChannelVetoSel[3] = {0, 0, 0};
466 __CFG_COUT__ <<
"Setting up output channels..." << std::endl;
468 std::array<std::string, 3> outChannelNames = {
"Channel0",
"Channel1",
"Channel2"};
469 for(
const auto& channelName : outChannelNames)
471 outputChannelSourceSelect =
472 theXDAQContextConfigTree_.getNode(theConfigurationPath_)
473 .getNode(
"TriggerInput" + channelName)
474 .getValue<
unsigned int>();
475 __CFG_COUT__ <<
"TriggerInput for " << channelName <<
" is "
476 << outputChannelSourceSelect << std::endl;
477 if(outputChannelSourceSelect)
479 --outputChannelSourceSelect;
481 if(usingOptionalParams)
483 outputDelay = optionalLink.getNode(
"DelayTriggerOutput" + channelName)
484 .getValue<
unsigned int>();
485 outputWidth = optionalLink.getNode(
"WidthTriggerOutput" + channelName)
486 .getValue<uint64_t>();
491 outputWidthMask = 64;
494 outputWidthMask = outputWidth;
497 outputModMask = (0xFFFFFFFFFFFFFFFF >> (64 - outputWidthMask))
503 outputTimeVetoDuration =
504 optionalLink.getNode(
"TimeVetoTriggerOutput" + channelName)
505 .getValue<
unsigned int>();
507 outputPrescaleCount =
508 optionalLink.getNode(
"PrescaleTriggerOutput" + channelName)
509 .getValue<
unsigned int>();
510 outputBackpressureSelect =
511 optionalLink.getNode(
"BackpressureTriggerOutput" + channelName)
513 gateChannelVetoSel[channelCount] =
514 optionalLink.getNode(
"VetoSourceTriggerOutput" + channelName)
516 __CFG_COUT__ <<
"Raw gateChannelVetoSelect for " << channelName <<
" is "
517 << gateChannelVetoSel[channelCount] << std::endl;
522 outputModMask = 0xFFF;
524 outputTimeVetoDuration = 0;
525 outputPrescaleCount = 0;
526 outputBackpressureSelect =
false;
529 if(gateChannelVetoSel[channelCount] <= 1)
530 gateChannelVetoSel[channelCount] = 4;
532 gateChannelVetoSel[channelCount] -= 2;
534 backpressureMask |= (outputBackpressureSelect ? 1 : 0) << channelCount;
536 OtsUDPFirmwareCore::writeAdvanced(
538 addrOffset + (channelCount == 0 ? 0x4 : (0x18016 + channelCount - 1)),
540 OtsUDPHardware::write(writeBuffer);
542 OtsUDPFirmwareCore::writeAdvanced(
544 addrOffset + (channelCount == 0 ? 0x2 : (0x18002 + channelCount - 1)),
546 OtsUDPHardware::write(writeBuffer);
548 OtsUDPFirmwareCore::writeAdvanced(
550 addrOffset + (0x106 + channelCount * 0x100),
551 outputWidth | (uint64_t(outputWidth ? 1 : 0 )
553 OtsUDPHardware::write(writeBuffer);
555 __CFG_COUT__ <<
"Output word for " << channelName <<
" is "
556 << std::bitset<64>(outputModMask) << std::endl;
557 __CFG_COUT__ <<
"Output delay of " << outputDelay
558 <<
" and an extended width of " << outputWidth << std::endl;
562 writeBuffer.resize(0);
563 OtsUDPFirmwareCore::writeAdvanced(
565 addrOffset + (0x18018 + channelCount - 1),
566 outputChannelSourceSelect);
568 OtsUDPHardware::write(writeBuffer);
569 __CFG_COUT__ <<
"Output src select is " << outputChannelSourceSelect
570 <<
" for " << channelName << std::endl;
574 writeBuffer.resize(0);
575 OtsUDPFirmwareCore::writeAdvanced(
577 addrOffset + (channelCount == 0 ? 0x1801B : (0x18011 + channelCount - 1)),
578 outputTimeVetoDuration);
579 OtsUDPHardware::write(writeBuffer);
581 __CFG_COUT__ <<
"Veto count for " << channelName <<
" is "
582 << outputTimeVetoDuration <<
" writing to ch "
583 << addrOffset + (channelCount == 0 ? 0x1801B : (0x18011 + channelCount - 1))
587 writeBuffer.resize(0);
588 OtsUDPFirmwareCore::writeAdvanced(
589 writeBuffer, addrOffset + (0x1801C + channelCount), 0);
590 OtsUDPHardware::write(writeBuffer);
591 writeBuffer.resize(0);
592 OtsUDPFirmwareCore::writeAdvanced(
593 writeBuffer, addrOffset + (0x1801C + channelCount), outputPrescaleCount);
594 OtsUDPHardware::write(writeBuffer);
596 __CFG_COUT__ <<
"Prescaler count for " << channelName <<
" is "
597 << outputPrescaleCount <<
" writing to ch "
598 << addrOffset + (0x1801C + channelCount) << std::endl;
608 __CFG_COUT__ <<
"Backpressure Selecting..." << std::endl;
609 outputBackpressureSelect =
610 usingOptionalParams &&
611 optionalLink.getNode(
"EnableBackPressureNwFmcPta1").getValue<
bool>();
612 backpressureMask |= outputBackpressureSelect << 3;
613 outputBackpressureSelect =
614 usingOptionalParams &&
615 optionalLink.getNode(
"EnableBackPressureNwFmcPta2").getValue<
bool>();
616 backpressureMask |= outputBackpressureSelect << 4;
617 writeBuffer.resize(0);
618 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1801A, backpressureMask);
619 OtsUDPHardware::write(writeBuffer);
622 OtsUDPFirmwareCore::writeAdvanced(
623 writeBuffer, addrOffset + 0x200, (uint64_t)-1);
624 OtsUDPHardware::write(writeBuffer);
627 __CFG_COUT__ <<
"Setting output muxes..." << std::endl;
628 unsigned int outputPolarityMask = 0;
629 bool outputInvertPolarity;
631 for(
const auto& channelName : v1channelNames)
633 outputMuxSelect = theXDAQContextConfigTree_.getNode(theConfigurationPath_)
634 .getNode(
"OutputMuxSelect" + channelName)
635 .getValue<
unsigned int>();
640 if(outputMuxSelect > 31)
643 throw std::runtime_error(ss.str() +
"Invalid output mux select!");
646 if(usingOptionalParams)
648 outputInvertPolarity =
649 usingOptionalParams &&
650 optionalLink.getNode(
"InvertPolarityOutput" + channelName)
652 outputPolarityMask |= ((outputInvertPolarity ? 1 : 0) << channelCount);
656 outputPolarityMask = 0xF;
659 writeBuffer.resize(0);
660 OtsUDPFirmwareCore::writeAdvanced(
662 addrOffset + (channelCount == 0 ? 0x5 : (0x18013 + channelCount - 1)),
664 OtsUDPHardware::write(writeBuffer);
665 __CFG_COUT__ <<
"Mux value for output channel " << channelName <<
" is "
666 << outputMuxSelect <<
", written to 0x" << std::hex
667 << addrOffset + (channelCount == 0 ? 0x5 : (0x18013 + channelCount - 1))
668 << std::dec << std::endl;
673 writeBuffer.resize(0);
674 OtsUDPFirmwareCore::writeAdvanced(
676 addrOffset + 0x1800C,
678 OtsUDPHardware::write(writeBuffer);
679 __CFG_COUT__ <<
"Output polarity mask is " << std::bitset<8>(outputPolarityMask)
683 if(usingOptionalParams)
700 uint64_t trigClkOutBankRegister = 0;
701 unsigned int bank = 0;
703 std::array<std::string, 2> trigClkOutBankNames = {
704 "TriggerMuxSelectionsBankA",
"TriggerMuxSelectionsBankB"};
705 for(
auto& trigClkOutBankName : trigClkOutBankNames)
707 __COUTV__(trigClkOutBankName);
709 ConfigurationTree::BitMap bankSelectionMap =
710 optionalLink.getNode(trigClkOutBankName).getValueAsBitMap();
715 unsigned int col = 0;
716 for(; col < 6; ++col)
717 trigClkOutBankRegister |=
718 (bankSelectionMap.get(0, col) & 0x3)
719 << ((bank * 6 + col) *
722 for(; col < 9; ++col)
723 trigClkOutBankRegister |=
724 (bankSelectionMap.get(0, col) & 0x3)
725 << ((12 + bank * 3 + col) *
731 OtsUDPFirmwareCore::writeAdvanced(
734 trigClkOutBankRegister);
735 OtsUDPHardware::write(writeBuffer);
740 __CFG_COUT__ <<
"Setting up Burst Data Blocks" << std::endl;
742 unsigned int logicSampleDelay = 0;
743 unsigned int gateChannel = 0;
744 unsigned int gateChannelReg =
745 (gateChannelVetoSel[2] << 8) | (gateChannelVetoSel[1] << 4) |
746 (gateChannelVetoSel[0] << 0);
748 __CFG_COUT__ <<
"Gate Ch Veto Selections - 2: " << gateChannelVetoSel[2]
750 __CFG_COUT__ <<
"Gate Ch Veto Selections - 1: " << gateChannelVetoSel[1]
752 __CFG_COUT__ <<
"Gate Ch Veto Selections - 0: " << gateChannelVetoSel[0]
757 if(usingOptionalParams)
760 optionalLink.getNode(
"BurstDataMuxSelect").getValue<
unsigned int>();
761 logicSampleDelay = optionalLink.getNode(
"BurstDataLogicSampleDelay")
762 .getValue<
unsigned int>();
763 gateChannel = optionalLink.getNode(
"BurstDataGateInputChannel")
764 .getValue<
unsigned int>();
777 gateChannelReg |= gateChannel << 12;
781 gateChannelReg |= 4 << 12;
783 __CFG_COUT__ <<
"Gate Ch Veto Selections - Burst: " << gateChannel
785 std::bitset<16> gateChannelRegBitset(gateChannelReg);
786 __CFG_COUT__ <<
"Gate Ch Veto Register: " << gateChannelReg << std::endl;
787 __CFG_COUT__ <<
"Gate Ch Veto Register: " << gateChannelRegBitset.to_string()
790 OtsUDPFirmwareCore::writeAdvanced(
791 writeBuffer, addrOffset + 0x1800E, outputMuxSelect);
792 OtsUDPHardware::write(writeBuffer);
794 OtsUDPFirmwareCore::writeAdvanced(
796 addrOffset + 0x18010,
798 OtsUDPHardware::write(writeBuffer);
800 OtsUDPFirmwareCore::writeAdvanced(
802 addrOffset + 0x18004,
804 OtsUDPHardware::write(writeBuffer);
806 if(outputMuxSelect == 1)
808 OtsUDPFirmwareCore::writeAdvanced(
809 writeBuffer, addrOffset + 0x1800F, 0x2);
810 OtsUDPHardware::write(writeBuffer);
814 OtsUDPFirmwareCore::writeAdvanced(
815 writeBuffer, addrOffset + 0x1800F, 0);
816 OtsUDPHardware::write(writeBuffer);
821 unsigned int coincidenceLogicWord =
822 theXDAQContextConfigTree_.getNode(theConfigurationPath_)
823 .getNode(
"CoincidenceLogicWord")
824 .getValue<
unsigned int>();
826 sel_ctl_register_ |= 1;
827 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x6, sel_ctl_register_);
828 OtsUDPHardware::write(writeBuffer);
829 __CFG_COUT__ <<
" sel_ctl_register_ 1: " << std::bitset<16>(sel_ctl_register_)
834 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x6, sel_ctl_register_);
835 OtsUDPHardware::write(writeBuffer);
836 __CFG_COUT__ <<
" sel_ctl_register_ 2: " << std::bitset<16>(sel_ctl_register_)
839 OtsUDPFirmwareCore::writeAdvanced(
840 writeBuffer, addrOffset + 0x7, coincidenceLogicWord);
841 OtsUDPHardware::write(writeBuffer);
842 __CFG_COUT__ <<
"Selection Logic word is bit: "
843 << std::bitset<16>(coincidenceLogicWord) << std::endl;
849 sel_ctl_register_ |= 1 << 1;
850 OtsUDPFirmwareCore::writeAdvanced(
851 writeBuffer, addrOffset + 0x6, sel_ctl_register_);
852 OtsUDPHardware::write(writeBuffer);
853 __CFG_COUT__ <<
" sel_ctl_register_: 3" << std::bitset<16>(sel_ctl_register_)
856 unsigned int sigGenCount =
857 optionalLink.getNode(
"SignalGeneratorPulseCount").getValue<
unsigned int>();
858 unsigned int sigGenHighPer =
859 optionalLink.getNode(
"SignalGeneratorHighPeriod").getValue<
unsigned int>();
860 unsigned int sigGenLowPer =
861 optionalLink.getNode(
"SignalGeneratorLowPeriod").getValue<
unsigned int>();
862 bool sigGenPolarity =
863 optionalLink.getNode(
"SignalGeneratorInvertPolarity").getValue<
bool>();
864 unsigned int sigGenPolarityMask = (sigGenPolarity ? 1 : 0);
866 if(optionalLink.getNode(
"SignalGeneratorEnable").getValue<
bool>())
869 OtsUDPFirmwareCore::writeAdvanced(
870 writeBuffer, addrOffset + 0x18000, nimResets_.to_ulong());
871 OtsUDPHardware::write(writeBuffer);
872 nimEnables_.reset(5);
873 OtsUDPFirmwareCore::writeAdvanced(
874 writeBuffer, addrOffset + 0x18001, nimEnables_.to_ulong());
875 OtsUDPHardware::write(writeBuffer);
877 __CFG_COUT__ <<
"Resets all for sig gen!" << std::endl;
880 writeBuffer.resize(0);
881 OtsUDPFirmwareCore::writeAdvanced(
882 writeBuffer, addrOffset + 0x18005, sigGenCount);
883 OtsUDPHardware::write(writeBuffer);
884 writeBuffer.resize(0);
885 OtsUDPFirmwareCore::writeAdvanced(
886 writeBuffer, addrOffset + 0x18006, sigGenHighPer);
887 OtsUDPHardware::write(writeBuffer);
888 writeBuffer.resize(0);
889 OtsUDPFirmwareCore::writeAdvanced(
890 writeBuffer, addrOffset + 0x18007, sigGenLowPer);
891 OtsUDPHardware::write(writeBuffer);
892 writeBuffer.resize(0);
893 OtsUDPFirmwareCore::writeAdvanced(
894 writeBuffer, addrOffset + 0x1800D, sigGenPolarityMask);
895 OtsUDPHardware::write(writeBuffer);
897 __CFG_COUT__ <<
"Configured signal generator with a count of " << sigGenCount
898 <<
" (0 is continuous output), a high period of "
899 << sigGenHighPer <<
", a low period of " << sigGenLowPer
900 <<
", and output inversion set to " << sigGenPolarity
910 nimEnables_.reset(5);
911 __CFG_COUT__ <<
"Signal Generator disabled" << std::endl;
914 OtsUDPFirmwareCore::writeAdvanced(
915 writeBuffer, addrOffset + 0x18000, nimResets_.to_ulong());
916 OtsUDPHardware::write(writeBuffer);
917 __CFG_COUT__ <<
"Nim Resets (after sig gen setup) set to " << nimResets_
920 OtsUDPFirmwareCore::writeAdvanced(
921 writeBuffer, addrOffset + 0x18001, nimEnables_.to_ulong());
922 OtsUDPHardware::write(writeBuffer);
923 __CFG_COUT__ <<
"Nim Enables (after sig gen setup) set to " << nimEnables_
926 catch(
const std::runtime_error& e)
928 __CFG_COUT__ <<
"Failed output stage setup!\n" << e.what() << std::endl;
932 __CFG_COUT__ <<
"Checking sel_ctl_register_... Expect sel_ctl_register_ = 0x"
933 << std::hex << sel_ctl_register_ << std::dec << std::endl;
936 OtsUDPFirmwareCore::readAdvanced(writeBuffer, addrOffset + 10 );
947 __CFG_COUT__ <<
"sel_ctl_register_ = 0x" << std::hex << sel_ctl_register_ << std::dec
953 __CFG_COUT__ <<
" sel_ctl_register_: " << std::bitset<16>(sel_ctl_register_)
956 __CFG_COUT__ <<
"Done with configuring." << std::endl;
960 void FENIMPlusInterface::halt(
void)
962 __CFG_COUT__ <<
"\tHalt" << std::endl;
967 void FENIMPlusInterface::pause(
void)
969 __CFG_COUT__ <<
"\tPause" << std::endl;
974 void FENIMPlusInterface::resume(
void)
976 __CFG_COUT__ <<
"\tResume" << std::endl;
981 void FENIMPlusInterface::start(std::string runNumber)
983 runNumber_ = runNumber;
984 __CFG_COUT__ <<
"\tStart " << runNumber_ << std::endl;
985 std::string writeBuffer;
990 __CFG_COUT__ <<
"Disabling sig_log" << std::endl;
991 OtsUDPFirmwareCore::writeAdvanced(
992 writeBuffer, addrOffset + 0x6, (sel_ctl_register_) & (~(1 << 1)));
993 OtsUDPHardware::write(writeBuffer);
995 __CFG_COUT__ <<
"Resetting all counters (including sig log)" << std::endl;
1000 OtsUDPFirmwareCore::writeAdvanced(
1001 writeBuffer, addrOffset + 0x18000, nimResets_.to_ulong());
1004 OtsUDPHardware::write(writeBuffer);
1007 OtsUDPFirmwareCore::writeAdvanced(
1008 writeBuffer, addrOffset + 0x18000, nimResets_.to_ulong());
1009 OtsUDPHardware::write(writeBuffer);
1011 ConfigurationTree optionalLink =
1012 theXDAQContextConfigTree_.getNode(theConfigurationPath_)
1013 .getNode(
"LinkToOptionalParameters");
1014 bool usingOptionalParams = !optionalLink.isDisconnected();
1016 if(usingOptionalParams && optionalLink.getNode(
"EnableBurstData").getValue<
bool>())
1018 __CFG_COUT__ <<
"Enabling burst mode!" << __E__;
1019 OtsUDPFirmwareCore::startBurst(writeBuffer);
1020 OtsUDPHardware::write(writeBuffer);
1024 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, 0x1801F, 0x6);
1025 OtsUDPHardware::write(writeBuffer);
1026 __CFG_COUT__ <<
"\tStart Done" << std::endl;
1030 void FENIMPlusInterface::stop(
void)
1032 std::string writeBuffer;
1034 OtsUDPFirmwareCore::writeAdvanced(
1035 writeBuffer, addrOffset + 0x6 , (sel_ctl_register_) & (~(1 << 1)));
1036 OtsUDPHardware::write(writeBuffer);
1038 __CFG_COUT__ <<
"\tStop" << std::endl;
1041 runSequenceOfCommands(
"LinkToStopSequence");
1044 OtsUDPFirmwareCore::stopBurst(writeBuffer);
1045 OtsUDPHardware::write(writeBuffer);
1047 uint64_t readQuadWord;
1049 ConfigurationTree optionalLink =
1050 theXDAQContextConfigTree_.getNode(theConfigurationPath_)
1051 .getNode(
"LinkToOptionalParameters");
1052 if(!optionalLink.isDisconnected())
1056 optionalLink.getNode(
"TriggerCountAtRunStopFilename").getValue<std::string>();
1058 if(filename !=
"DEFAULT" && filename !=
"")
1060 std::string filename = optionalLink.getNode(
"TriggerCountAtRunStopFilename")
1061 .getValue<std::string>();
1063 if(filename !=
"DEFAULT" && filename !=
"")
1065 filename +=
"_" + runNumber_ +
".cnt";
1067 __CFG_COUT__ <<
"Attempting to save counts to " << filename << __E__;
1075 __CFG_COUT__ <<
"Saving counts to " << filename << __E__;
1081 OtsUDPFirmwareCore::readAdvanced(writeBuffer, addrOffset + 0x102);
1082 OtsUDPHardware::read(writeBuffer, readQuadWord);
1084 count = (readQuadWord >> 32);
1086 count = (count & 0x0FFFFFFF);
1087 __CFG_COUT__ <<
"sig_log count = " << count << __E__;
1088 fprintf(fp,
"sig_log \t [tag=%d] %d 0x%4.4X\n", tag, count, count);
1090 count = (readQuadWord & 0x0FFFFFFFF);
1092 count = (count & 0x0FFFFFFF);
1093 __CFG_COUT__ <<
"sig_norm(out0) count = " << count << __E__;
1095 fp,
"sig_norm(out0) \t [tag=%d] %d 0x%4.4X\n", tag, count, count);
1097 OtsUDPFirmwareCore::readAdvanced(writeBuffer, addrOffset + 0x100);
1098 OtsUDPHardware::read(writeBuffer, readQuadWord);
1100 count = (readQuadWord & 0x0FFFFFFFF);
1102 count = (count & 0x0FFFFFFF);
1103 __CFG_COUT__ <<
"sig_cms1(out1) count = " << count << __E__;
1105 fp,
"sig_cms1(out1) \t [tag=%d] %d 0x%4.4X\n", tag, count, count);
1107 count = (readQuadWord >> 32);
1109 count = (count & 0x0FFFFFFF);
1110 __CFG_COUT__ <<
"sig_cms2(out2) count = " << count << __E__;
1112 fp,
"sig_cms2(out2) \t [tag=%d] %d 0x%4.4X\n", tag, count, count);
1114 OtsUDPFirmwareCore::readAdvanced(writeBuffer, addrOffset + 0x105);
1115 OtsUDPHardware::read(writeBuffer, readQuadWord);
1117 count = (readQuadWord & 0x0FFFFFFFF);
1119 count = (count & 0x0FFFFFFF);
1120 __CFG_COUT__ <<
"muxout-A count = " << count << __E__;
1121 fprintf(fp,
"muxout-A \t [tag=%d] %d 0x%4.4X\n", tag, count, count);
1123 count = (readQuadWord >> 32);
1125 count = (count & 0x0FFFFFFF);
1126 __CFG_COUT__ <<
"muxout-B count = " << count << __E__;
1127 fprintf(fp,
"muxout-B \t [tag=%d] %d 0x%4.4X\n", tag, count, count);
1129 OtsUDPFirmwareCore::readAdvanced(writeBuffer, addrOffset + 0x106);
1130 OtsUDPHardware::read(writeBuffer, readQuadWord);
1132 count = (readQuadWord & 0x0FFFFFFFF);
1134 count = (count & 0x0FFFFFFF);
1135 __CFG_COUT__ <<
"muxout-C count = " << count << __E__;
1136 fprintf(fp,
"muxout-C \t [tag=%d] %d 0x%4.4X\n", tag, count, count);
1138 count = (readQuadWord >> 32);
1140 count = (count & 0x0FFFFFFF);
1141 __CFG_COUT__ <<
"muxout-D count = " << count << __E__;
1142 fprintf(fp,
"muxout-D \t [tag=%d] %d 0x%4.4X\n", tag, count, count);
1145 OtsUDPFirmwareCore::readAdvanced(writeBuffer,addrOffset + 0x10);
1146 OtsUDPHardware::read(writeBuffer, readQuadWord);
1148 __CFG_COUT__ <<
"Clocks lock loss " << count << __E__;
1150 count = (((readQuadWord >> 24) & 0xF) >> 0) & 1;
1152 fp,
"DAC Clock-Lock-Loss \t %d 0x%4.4X\n", count, count);
1153 count = (((readQuadWord >> 24) & 0xF) >> 1) & 1;
1155 fp,
"Main Clock-Lock-Loss \t %d 0x%4.4X\n", count, count);
1156 count = (((readQuadWord >> 24) & 0xF) >> 2) & 1;
1158 fp,
"External Clock-Lock-Loss \t %d 0x%4.4X\n", count, count);
1159 count = (((readQuadWord >> 24) & 0xF) >> 3) & 1;
1161 fp,
"OutPhase Clock-Lock-Loss \t %d 0x%4.4X\n", count, count);
1171 writeBuffer.resize(0);
1172 OtsUDPFirmwareCore::writeAdvanced(
1173 writeBuffer, addrOffset + 0x4, 0x33);
1176 OtsUDPHardware::write(writeBuffer);
1180 bool FENIMPlusInterface::running(
void)
1182 std::string writeBuffer;
1190 __CFG_COUT__ <<
"Running" << std::endl;
1191 __CFG_COUT__ <<
" sel_ctl_register_: " << std::bitset<16>(sel_ctl_register_)
1197 ConfigurationTree optionalLink =
1198 theXDAQContextConfigTree_.getNode(theConfigurationPath_)
1199 .getNode(
"LinkToOptionalParameters");
1200 bool usingOptionalParams = !optionalLink.isDisconnected();
1205 unsigned int sleepSeconds = 0;
1206 if(usingOptionalParams)
1210 sleepSeconds = optionalLink.getNode(
"SecondsDelayBeforeStartingTriggers")
1211 .getValue<
unsigned int>();
1216 <<
"Ingore missing SecondsDelayBeforeStartingTriggers field..."
1218 }
void changeDACLevelv2(
const std::string& channelName,
unsigned int value);
1222 __CFG_COUT__ <<
"Sleeping for " << sleepSeconds <<
" seconds..." << __E__;
1223 sleep(sleepSeconds);
1225 unsigned char channelCount = 0;
1226 bool enable40MHzMask;
1227 unsigned int gateChannelVetoSel;
1230 std::array<std::string, 3> outChannelNames = {
"Channel0",
"Channel1",
"Channel2"};
1232 __CFG_COUT__ <<
"Enabling output trigger channels!" << std::endl;
1235 for(channelCount = 2; channelCount <= 2; --channelCount)
1238 usingOptionalParams && optionalLink
1239 .getNode(
"EnableClockMaskTriggerOutput" +
1240 outChannelNames[channelCount])
1242 gateChannelVetoSel = usingOptionalParams
1244 .getNode(
"VetoSourceTriggerOutput" +
1245 outChannelNames[channelCount])
1249 OtsUDPFirmwareCore::writeAdvanced(
1251 addrOffset + (channelCount == 0 ? 0x4 : (0x18016 + channelCount - 1)),
1252 (enable40MHzMask ? 0x0 : 0x8) |
1253 (gateChannelVetoSel <= 1
1256 OtsUDPHardware::write(writeBuffer);
1259 __CFG_COUT__ <<
"Enabling siglog block!" << __E__;
1260 __CFG_COUT__ <<
" sel_ctl_register_: " << std::bitset<16>(sel_ctl_register_)
1262 OtsUDPFirmwareCore::writeAdvanced(
1268 OtsUDPHardware::write(writeBuffer);
1270 catch(
const std::runtime_error& e)
1272 __SS__ <<
"Failed start setup!\n" << e.what() << std::endl;
1273 __CFG_COUT_ERR__ << ss.str();
1274 throw std::runtime_error(ss.str());
1313 void FENIMPlusInterface::FEMacroGenerateTriggers(__ARGS__)
1315 __CFG_COUT__ <<
"FEMacroGenerateTriggers" << __E__;
1317 unsigned int numberOfTriggers = __GET_ARG_IN__(
"numberOfTriggers",
unsigned int);
1318 unsigned int signalHiDuration = __GET_ARG_IN__(
"signalHiDuration",
unsigned int);
1319 unsigned int signalLoDuration = __GET_ARG_IN__(
"signalLoDuration",
unsigned int);
1320 std::string& triggersWereLaunched =
1321 getFEMacroArgument(argsOut,
"triggersWereLaunched");
1322 std::string numberOfTriggersStr = __GET_ARG_IN__(
"numberOfTriggers", std::string);
1324 __CFG_COUTV__(numberOfTriggers);
1325 __CFG_COUTV__(signalHiDuration);
1326 __CFG_COUTV__(signalLoDuration);
1327 __CFG_COUTV__(numberOfTriggersStr);
1331 std::string writeBuffer;
1334 nimEnables_.reset(5);
1335 OtsUDPFirmwareCore::writeAdvanced(
1336 writeBuffer, addrOffset + 0x18001, nimEnables_.to_ulong());
1337 OtsUDPHardware::write(writeBuffer);
1338 __CFG_COUT__ <<
"Nim Enables set to 0x" << std::hex << nimEnables_ << std::dec
1346 OtsUDPFirmwareCore::writeAdvanced(
1347 writeBuffer, addrOffset + 0x18005, nimEnables_.to_ulong());
1348 OtsUDPHardware::write(writeBuffer);
1349 __CFG_COUT__ <<
"Nim Enables set to 0x" << std::hex << nimEnables_ << std::dec
1358 OtsUDPFirmwareCore::writeAdvanced(
1359 writeBuffer, addrOffset + 0x18001, numberOfTriggers);
1360 OtsUDPHardware::write(writeBuffer);
1361 __CFG_COUT__ <<
"Nim Enables set to 0x" << std::hex << nimEnables_ << std::dec
1365 __CFG_COUT__ <<
"triggersWereLaunched " << triggersWereLaunched << __E__;
1366 triggersWereLaunched =
"Done!";
1367 __CFG_COUT__ <<
"triggersWereLaunched " << triggersWereLaunched << __E__;
1368 __SET_ARG_OUT__(
"triggersWereLaunched", 42.2f);
1369 __CFG_COUT__ <<
"triggersWereLaunched " << triggersWereLaunched << __E__;
1370 __SET_ARG_OUT__(
"triggersWereLaunched", 42.2f);
1371 __CFG_COUT__ <<
"triggersWereLaunched " << triggersWereLaunched << __E__;
1375 void FENIMPlusInterface::changeDACLevelv1(
const std::string& channelName,
unsigned int dacValue)
1377 std::string writeBuffer;
1381 std::map<std::string, unsigned int> channelNameToAddressMap;
1382 channelNameToAddressMap[
"ChannelA"] = 0x6;
1383 channelNameToAddressMap[
"ChannelB"] = 0xe;
1384 channelNameToAddressMap[
"ChannelC"] = 0x2;
1385 channelNameToAddressMap[
"ChannelD"] = 0xa;
1388 const std::string dacValueField =
"DACValue";
1389 writeBuffer.resize(0);
1390 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1391 OtsUDPHardware::write(writeBuffer);
1400 writeBuffer.resize(0);
1401 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x0, (channelNameToAddressMap[channelName] << 12) | (dacValue & 0xFFF));
1402 OtsUDPHardware::write(writeBuffer);
1404 writeBuffer.resize(0);
1405 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x2);
1406 OtsUDPHardware::write(writeBuffer);
1407 writeBuffer.resize(0);
1408 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1409 OtsUDPHardware::write(writeBuffer);
1410 writeBuffer.resize(0);
1411 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x4);
1412 OtsUDPHardware::write(writeBuffer);
1413 writeBuffer.resize(0);
1414 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1415 OtsUDPHardware::write(writeBuffer);
1420 void FENIMPlusInterface::changeDACLevelv2(
const std::string& channelName,
unsigned int dacValue)
1422 std::string writeBuffer;
1426 std::map<std::string, unsigned int> channelNameToAddressMap;
1433 channelNameToAddressMap[
"ChannelA"] = 0x0;
1434 channelNameToAddressMap[
"ChannelB"] = 0x1;
1435 channelNameToAddressMap[
"ChannelC"] = 0x2;
1436 channelNameToAddressMap[
"ChannelD"] = 0x3;
1437 channelNameToAddressMap[
"ChannelE"] = 0x4;
1438 channelNameToAddressMap[
"ChannelF"] = 0x5;
1439 channelNameToAddressMap[
"ChannelG"] = 0x6;
1440 channelNameToAddressMap[
"ChannelH"] = 0x7;
1441 const std::string dacValueField =
"DACValue";
1442 writeBuffer.resize(0);
1443 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1444 OtsUDPHardware::write(writeBuffer);
1453 writeBuffer.resize(0);
1454 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x0, (channelNameToAddressMap[channelName] << 12) | (dacValue & 0xFFF));
1455 OtsUDPHardware::write(writeBuffer);
1457 writeBuffer.resize(0);
1458 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x2);
1459 OtsUDPHardware::write(writeBuffer);
1460 writeBuffer.resize(0);
1461 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1462 OtsUDPHardware::write(writeBuffer);
1463 writeBuffer.resize(0);
1464 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x4);
1465 OtsUDPHardware::write(writeBuffer);
1466 writeBuffer.resize(0);
1467 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1468 OtsUDPHardware::write(writeBuffer);
1473 void FENIMPlusInterface::initDAC(
void)
1475 std::string writeBuffer;
1477 writeBuffer.resize(0);
1478 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x0, 0xF000);
1479 OtsUDPHardware::write(writeBuffer);
1480 writeBuffer.resize(0);
1481 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x2);
1482 OtsUDPHardware::write(writeBuffer);
1483 writeBuffer.resize(0);
1484 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1485 OtsUDPHardware::write(writeBuffer);
1486 writeBuffer.resize(0);
1487 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x4);
1488 OtsUDPHardware::write(writeBuffer);
1489 writeBuffer.resize(0);
1490 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1491 OtsUDPHardware::write(writeBuffer);
1493 writeBuffer.resize(0);
1494 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x0, 0x8003);
1495 OtsUDPHardware::write(writeBuffer);
1496 writeBuffer.resize(0);
1497 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x2);
1498 OtsUDPHardware::write(writeBuffer);
1499 writeBuffer.resize(0);
1500 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1501 OtsUDPHardware::write(writeBuffer);
1502 writeBuffer.resize(0);
1503 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x4);
1504 OtsUDPHardware::write(writeBuffer);
1505 writeBuffer.resize(0);
1506 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1507 OtsUDPHardware::write(writeBuffer);
1509 writeBuffer.resize(0);
1510 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x0, 0xA001);
1511 OtsUDPHardware::write(writeBuffer);
1512 writeBuffer.resize(0);
1513 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x2);
1514 OtsUDPHardware::write(writeBuffer);
1515 writeBuffer.resize(0);
1516 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1517 OtsUDPHardware::write(writeBuffer);
1518 writeBuffer.resize(0);
1519 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x4);
1520 OtsUDPHardware::write(writeBuffer);
1521 writeBuffer.resize(0);
1522 OtsUDPFirmwareCore::writeAdvanced(writeBuffer, addrOffset + 0x1, 0x0);
1523 OtsUDPHardware::write(writeBuffer);