otsdaq_prepmodernization  v2_05_00
GEC_TX_CTL_0.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : GEC_TX_CTL_0
4 -- Design : CAPTAN
5 -- Author : aprosser
6 -- Company : CD_CEPA_ESE
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : u:\CAPTAN\Data_Conversion_Board\CAPTAN\CAPTAN\compile\GEC_TX_CTL_0.vhd
11 -- Generated : 06/11/08 15:13:34
12 -- From : u:/CAPTAN/Data_Conversion_Board/CAPTAN/CAPTAN/src/GEC_TX_CTL_0.asf
13 -- By : FSM2VHDL ver. 5.0.0.9
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_arith.all;
24 use IEEE.std_logic_unsigned.all;
25 use params_package.all;
26 
27 entity gec_tx_ctl_0 is
28  port (
29  block_en: in STD_LOGIC;
30  clk: in STD_LOGIC;
31  data_fifo_empty: in STD_LOGIC;
32  data_fifo_rderr: in STD_LOGIC;
33  gec_user_busy: in STD_LOGIC;
34  gec_user_tx_enable_out: in STD_LOGIC;
35  info_fifo_empty: in STD_LOGIC;
36  info_fifo_rd_data: in STD_LOGIC_VECTOR (15 downto 0);
37  info_fifo_rderr: in STD_LOGIC;
38  reset_n: in STD_LOGIC;
39  data_fifo_rden: out STD_LOGIC;
40  data_fifo_rden_en: out STD_LOGIC;
41  gec_user_trigger: out STD_LOGIC;
42  gec_user_tx_size_in: out STD_LOGIC_VECTOR (10 downto 0);
43  info_fifo_rden: out STD_LOGIC);
44 end gec_tx_ctl_0;
45 
46 architecture gec_tx_ctl_0 of GEC_TX_CTL_0 is
47 
48 -- diagram signals declarations
49 signal tx_data_count: STD_LOGIC_VECTOR (10 downto 0);
50 
51 -- SYMBOLIC ENCODED state machine: Sreg0
52 type Sreg0_type is (
53  idle, enabled, chk_busy, txmtdone, data_rdy_read_Ififo, trgrd, data_rdy_savecount, txmt_xmiting, txmt_last_byte
54 );
55 -- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding
56 
57 signal Sreg0: Sreg0_type;
58 
59 begin
60 
61 
62 ----------------------------------------------------------------------
63 -- Machine: Sreg0
64 ----------------------------------------------------------------------
65 Sreg0_machine: process (clk)
66 begin
67  if clk'event and clk = '1' then
68  if reset_n = '0' then
69  Sreg0 <= idle;
70  -- Set default values for outputs, signals and variables
71  -- ...
72  gec_user_trigger <= '0';
73  gec_user_tx_size_in <= v_11_0;
74  tx_data_count <= v_11_0;
75  info_fifo_rden <= '0';
76  data_fifo_rden <= '0';
77  data_fifo_rden_en <= '0';
78  else
79  -- Set default values for outputs, signals and variables
80  -- ...
81  case Sreg0 is
82  when idle =>
83  if block_en = '0' then
84  Sreg0 <= idle;
85  elsif block_en = '1' then
86  Sreg0 <= enabled;
87  end if;
88  when enabled =>
89  if info_fifo_empty = '0' and block_en = '1' then -- FIFO has an entry
90  Sreg0 <= data_rdy_read_Ififo;
91  info_fifo_rden <= '1';
92  -- Read the info word
93  data_fifo_rden_en <= '1';
94  -- this enables the OR'd
95  -- conbination of user_tx_enable_out
96  -- and data_fifo_rden
97  elsif block_en = '0' then
98  Sreg0 <= idle;
99  elsif info_fifo_empty = '1' and block_en = '1' then -- FIFO is empty
100  Sreg0 <= enabled;
101  end if;
102  when chk_busy =>
103  if gec_user_busy = '0' then
104  Sreg0 <= trgrd;
105  gec_user_trigger <= '1';
106  -- GEC not busy
107  -- assert trigger to GEC
108  elsif gec_user_busy = '1' then
109  Sreg0 <= chk_busy;
110  end if;
111  when txmtdone =>
112  if block_en = '1' then
113  Sreg0 <= enabled;
114  elsif block_en = '0' then
115  Sreg0 <= idle;
116  end if;
117  when trgrd =>
118  if gec_user_tx_enable_out = '0' then -- wait for enable tx reply
119  Sreg0 <= trgrd;
120  elsif gec_user_tx_enable_out = '1' then
121  Sreg0 <= txmt_xmiting;
122  if (tx_data_count = v_11_1) then
123  data_fifo_rden_en <= '0';
124  -- turn off FIFO accesses early
125  -- only one byte is requested and
126  -- it has been preloaded (this should
127  -- not happen in loopback tests
128  else
129  tx_data_count <= tx_data_count - v_11_1;
130  end if;
131  -- decrement count of bytes;
132  -- user_tx_enable_out from the GEC is
133  -- enabling read operations on the data
134  -- FIFO
135  end if;
136  when data_rdy_read_Ififo =>
137  Sreg0 <= data_rdy_savecount;
138  info_fifo_rden <= '0';
139  -- terminate info word read
140  data_fifo_rden <= '1';
141  -- read the first data byte for preset
142  when data_rdy_savecount =>
143  Sreg0 <= chk_busy;
144  gec_user_tx_size_in <= info_fifo_rd_data(10 downto 0);
145  -- Present transmit size to GEC
146  data_fifo_rden <= '0';
147  -- terminate first data word read
148  -- Data should be present at the output
149  -- of the data FIFO (and the input to the
150  -- GEC)
151  tx_data_count <= info_fifo_rd_data(10 downto 0);
152  -- initialize byte count for transmission
153  -- Last byte with error codes for end
154  -- of transmission has already been put
155  -- into the data FIFO.
156  when txmt_xmiting =>
157  if tx_data_count = v_11_1 then
158  Sreg0 <= txmt_last_byte;
159  data_fifo_rden_en <= '0';
160  -- disable read enable control to
161  -- data FIFO
162  elsif tx_data_count /= v_11_1 then
163  Sreg0 <= txmt_xmiting;
164  tx_data_count <= tx_data_count - v_11_1;
165  -- decrement count of bytes
166  end if;
167  when txmt_last_byte =>
168  Sreg0 <= txmtdone;
169  gec_user_trigger <= '0';
170  gec_user_tx_size_in <= v_11_0;
171  tx_data_count <= v_11_0;
172  info_fifo_rden <= '0';
173  data_fifo_rden <= '0';
174  data_fifo_rden_en <= '0';
175  when others =>
176  null;
177  end case;
178  end if;
179  end if;
180 end process;
181 
182 end GEC_TX_CTL_0;