otsdaq_prepmodernization  v2_05_00
burst_traffic_controller.vhd
1 
2  library IEEE;
3  use IEEE.STD_LOGIC_1164.ALL;
4  use IEEE.STD_LOGIC_ARITH.ALL;
5  use IEEE.STD_LOGIC_UNSIGNED.ALL;
6 
7  use params_package.ALL;
8 
9 
11  port (
12 
13  MASTER_CLK : in std_logic; -- 125 MHz Ethernet Clock
14  RESET : in std_logic;
15 
16  BURST_END_PACKET: out std_logic;
17  BURST_WE: in std_logic
18 
19  );
20  end burst_traffic_controller;
21 
22 
23  architecture burst_traffic_controller_arch of burst_traffic_controller is
24 
25  signal clocks_since_send : std_logic_vector(33 downto 0);
26  signal writes_in_curr_burst : std_logic_vector(7 downto 0);
27 
28  begin
29 
30  process(MASTER_CLK)
31  begin
32 
33  if rising_edge(MASTER_CLK) then
34 
35  -- keep pulses to only one clock
36  BURST_END_PACKET <= '0';
37 
38  if reset = '1' then
39 
40  clocks_since_send <= (others => '0');
41  writes_in_curr_burst <= (others => '0');
42 
43  else -- main section
44 
45  if clocks_since_send /= '1' & x"00000000" then -- increment clocks since last burst packet send
46  clocks_since_send <= clocks_since_send + 1;
47  end if;
48 
49  if BURST_WE = '1' then
50 
51  if writes_in_curr_burst >= 181 then
52  writes_in_curr_burst <= (others => '0');
53  clocks_since_send <= (others => '0');
54  else
55  writes_in_curr_burst <= writes_in_curr_burst + 1;
56  end if;
57 
58  else
59 
60  -- check if between hits should end Burst Packet due to time out period
61  if writes_in_curr_burst /= 0 and
62  clocks_since_send >= '0' & x"0080" & '1' & x"E848" then--BURST_PERIOD_MAX & '1' & x"E848" then -- in ms : [<val> * 0x1E848] 125Mhz clocks is max wait
63  BURST_END_PACKET <= '1'; -- force end burst packet
64  clocks_since_send <= (others => '0');
65  writes_in_curr_burst <= (others => '0');
66  end if;
67 
68  end if;
69 
70  end if;
71 
72  end if;
73 
74  end process;
75 
76 
77  end architecture;