otsdaq_prepmodernization  v2_05_00
RAM_COMM_DEC_9.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : RAM_COMM_DEC_9
4 -- Design : ethernet_controller
5 -- Author : aprosser
6 -- Company : CD_CEPA_ESE
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : c:\HDL_Designs\dig_gec\ethernet_controller\compile\RAM_COMM_DEC_9.vhd
11 -- Generated : 03/20/09 15:19:35
12 -- From : c:/HDL_Designs/dig_gec/ethernet_controller/src/RAM_COMM_DEC_9.asf
13 -- By : FSM2VHDL ver. 5.0.5.6
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_arith.all;
24 use IEEE.std_logic_unsigned.all;
25 use params_package.all;
26 
27 entity RAM_COMM_DEC_9 is
28  port (
29  block_en: in STD_LOGIC;
30  burst_done: in STD_LOGIC;
31  clock: in STD_LOGIC;
32  reset_n: in STD_LOGIC;
33  rx_data_fifo_rd_data: in STD_LOGIC_VECTOR (63 downto 0);
34  rx_info_fifo_empty: in STD_LOGIC;
35  rx_info_fifo_rd_data: in STD_LOGIC_VECTOR (15 downto 0);
36  tx_info_fifo_full: in STD_LOGIC;
37  burst_start: out STD_LOGIC;
38  burst_stop: out STD_LOGIC;
39  ram_addr: out STD_LOGIC_VECTOR (63 downto 0);
40  ram_en: out STD_LOGIC;
41  ram_wren: out STD_LOGIC;
42  rx_data_fifo_rden: out STD_LOGIC;
43  Rx_FIFO_Reset: out STD_LOGIC;
44  rx_info_fifo_rden: out STD_LOGIC;
45  state_diag: out STD_LOGIC_VECTOR (0 to 5);
46  tx_data_fifo_src_sel: out STD_LOGIC;
47  tx_data_fifo_wren: out STD_LOGIC;
48  Tx_FIFO_Reset: out STD_LOGIC;
49  tx_info_fifo_src_sel: out STD_LOGIC;
50  tx_info_fifo_wr_data: out STD_LOGIC_VECTOR (15 downto 0);
51  tx_info_fifo_wren: out STD_LOGIC);
52 end RAM_COMM_DEC_9;
53 
54 architecture RAM_COMM_DEC_9 of RAM_COMM_DEC_9 is
55 
56 -- diagram signals declarations
57 signal burst_active: STD_LOGIC;
58 signal burst_complete_flag: STD_LOGIC;
59 signal comm_reg: STD_LOGIC_VECTOR (2 downto 0);
60 signal crc_err: STD_LOGIC;
61 signal mem_loc_count_reg: STD_LOGIC_VECTOR (7 downto 0);
62 signal q_w_count_reg: STD_LOGIC_VECTOR (7 downto 0);
63 signal ram_addr_reg: STD_LOGIC_VECTOR (63 downto 0);
64 
65 -- BINARY ENCODED state machine: Sreg0
66 attribute enum_encoding: string;
67 type Sreg0_type is (
68  dec_comm, enabled, idle, illegal, return_st, get_comm, write_com_S9, write_com_S8, write_com_S10, read_com_S13, read_com_S14, read_com_S15,
69  read_com_S16, read_com_S1, pro_comm, read_com_S18, write_com_S19, write_com_S11, write_com_S21, err_dec, crcerr_S24, crcerr_S25,
70  crcerr_S26, crcerr_S27, crcerr_S28, burst_strt_S30, burst_strt_S31, burst_strt_S33, burst_strt_S34, burst_stp_S36, burst_stp_S37,
71  burst_stp_S38, burst_stp_S39, brst_wait
72 );
73 attribute enum_encoding of Sreg0_type: type is
74  "000000 " & -- dec_comm
75  "000001 " & -- enabled
76  "000010 " & -- idle
77  "000011 " & -- illegal
78  "000100 " & -- return_st
79  "000101 " & -- get_comm
80  "000110 " & -- write_com_S9
81  "000111 " & -- write_com_S8
82  "001000 " & -- write_com_S10
83  "001001 " & -- read_com_S13
84  "001010 " & -- read_com_S14
85  "001011 " & -- read_com_S15
86  "001100 " & -- read_com_S16
87  "001101 " & -- read_com_S1
88  "001110 " & -- pro_comm
89  "001111 " & -- read_com_S18
90  "010000 " & -- write_com_S19
91  "010001 " & -- write_com_S11
92  "010010 " & -- write_com_S21
93  "010011 " & -- err_dec
94  "010100 " & -- crcerr_S24
95  "010101 " & -- crcerr_S25
96  "010110 " & -- crcerr_S26
97  "010111 " & -- crcerr_S27
98  "011000 " & -- crcerr_S28
99  "011001 " & -- burst_strt_S30
100  "011010 " & -- burst_strt_S31
101  "011011 " & -- burst_strt_S33
102  "011100 " & -- burst_strt_S34
103  "011101 " & -- burst_stp_S36
104  "011110 " & -- burst_stp_S37
105  "011111 " & -- burst_stp_S38
106  "100000 " & -- burst_stp_S39
107  "100001" ; -- brst_wait
108 
109 signal Sreg0: Sreg0_type;
110 
111 attribute state_vector: string;
112 attribute state_vector of RAM_COMM_DEC_9: architecture is "Sreg0";
113 
114 begin
115 
116 
117 ----------------------------------------------------------------------
118 -- Machine: Sreg0
119 ----------------------------------------------------------------------
120 Sreg0_machine: process (clock)
121 begin
122  if clock'event and clock = '1' then
123  if reset_n = '0' then
124  Sreg0 <= idle;
125  -- Set default values for outputs, signals and variables
126  -- ...
127 -- Initialize registers
128  comm_reg <= v_3_0;
129  q_w_count_reg <= v_8_0;
130  mem_loc_count_reg <= v_8_0;
131  burst_active <= '0';
132  crc_err <= '0';
133  ram_addr_reg <= v_64_0;
134 -- Initialize outputs
135  tx_info_fifo_wr_data <= v_16_0;
136  tx_info_fifo_wren <= '0';
137  tx_data_fifo_wren <= '0';
138 -- mux controls
139  tx_data_fifo_src_sel <= '0';
140  tx_info_fifo_src_sel <= '0';
141 -- ram controls
142  ram_addr <= v_64_0;
143  ram_wren <= '0';
144  ram_en <= '0';
145  burst_start <= '0';
146  burst_stop <= '0';
147  rx_info_fifo_rden <= '0';
148  rx_data_fifo_rden <= '0';
149  Rx_FIFO_Reset <= '1';
150  -- Reset FIFOs
151  burst_complete_flag <= '0';
152  else
153  -- Set default values for outputs, signals and variables
154  -- ...
155  case Sreg0 is
156  when dec_comm =>
157  if comm_reg(2) = '1' or
158  (comm_reg = "000" and burst_active = '1') or
159  (comm_reg = "010" and burst_active = '1') then
160  Sreg0 <= illegal;
161  Rx_FIFO_Reset <= '1';
162  elsif comm_reg = "010" and burst_active = '0' then
163  Sreg0 <= burst_strt_S33;
164  burst_active <= '1';
165  burst_start <= '1';
166  -- Point FIFO muxes towards
167  -- burst controller
168  tx_data_fifo_src_sel <= '1';
169  tx_info_fifo_src_sel <= '1';
170  if (burst_complete_flag = '1') then
171  Tx_FIFO_Reset <= '1';
172  end if;
173  elsif comm_reg = "011" then
174  Sreg0 <= burst_stp_S38;
175  burst_stop <= '1';
176  elsif comm_reg = "000" and burst_active = '0' then
177  Sreg0 <= read_com_S1;
178  if (burst_complete_flag = '1') then
179  Tx_FIFO_Reset <= '1';
180  end if;
181  elsif comm_reg = "001" then
182  Sreg0 <= write_com_S8;
183  rx_data_fifo_rden <= '1';
184  end if;
185  when enabled =>
186  if block_en = '0' then
187  Sreg0 <= idle;
188  elsif burst_done = '1' and
189  burst_active = '1' then
190  Sreg0 <= brst_wait;
191  elsif rx_info_fifo_empty = '0' then
192  Sreg0 <= get_comm;
193  rx_info_fifo_rden <= '1';
194  elsif rx_info_fifo_empty = '1' then
195  Sreg0 <= enabled;
196  end if;
197  when idle =>
198  if block_en = '0' then
199  Sreg0 <= idle;
200  Rx_FIFO_Reset <= '0';
201  -- disable reset
202  elsif block_en = '1' then
203  Sreg0 <= enabled;
204  Rx_FIFO_Reset <= '0';
205  end if;
206  when illegal =>
207  Sreg0 <= return_st;
208  Rx_FIFO_Reset <= '0';
209  when return_st =>
210  if block_en = '1' then
211  Sreg0 <= enabled;
212  elsif block_en = '0' then
213  Sreg0 <= idle;
214  end if;
215  when get_comm =>
216  Sreg0 <= pro_comm;
217  rx_info_fifo_rden <= '0';
218  when pro_comm =>
219  Sreg0 <= err_dec;
220  comm_reg <= rx_info_fifo_rd_data(2 downto 0);
221  -- Get the command code from
222  -- the receive info fifo word
223  q_w_count_reg <= rx_info_fifo_rd_data(15 downto 8);
224  -- get the number of 8 byte quad words from
225  -- the info fifo word
226  crc_err <= rx_info_fifo_rd_data(3);
227  -- get the crc error indicator
228  mem_loc_count_reg <= v_8_0;
229  when err_dec =>
230  if crc_err = '1' then
231  Sreg0 <= crcerr_S26;
232  rx_data_fifo_rden <= '1';
233  elsif crc_err = '0' then
234  Sreg0 <= dec_comm;
235  end if;
236  when brst_wait =>
237  if burst_done = '0' then
238  Sreg0 <= brst_wait;
239  elsif burst_done = '1' then
240  Sreg0 <= return_st;
241  burst_active <= '0';
242  burst_stop <= '0';
243  -- Point FIFO muxes towards
244  -- burst controller
245  tx_data_fifo_src_sel <= '0';
246  tx_info_fifo_src_sel <= '0';
247  burst_complete_flag <= '1';
248  end if;
249  when burst_stp_S36 =>
250  Sreg0 <= burst_stp_S37;
251  rx_data_fifo_rden <= '0';
252  when burst_stp_S37 =>
253  Sreg0 <= burst_stp_S39;
254  ram_addr_reg <= rx_data_fifo_rd_data;
255  -- obtain starting address
256  when burst_stp_S38 =>
257  Sreg0 <= burst_stp_S36;
258  -- there is at least one quad word in the data fifo
259  rx_data_fifo_rden <= '1';
260  when burst_stp_S39 =>
261  Sreg0 <= brst_wait;
262  ram_addr <= ram_addr_reg;
263  when read_com_S13 =>
264  Sreg0 <= read_com_S16;
265  ram_addr <= ram_addr_reg;
266  ram_en <= '1';
267  -- Enable the RAM
268  ram_addr_reg <= ram_addr_reg + v_64_1;
269  mem_loc_count_reg <= mem_loc_count_reg + v_8_1;
270  when read_com_S14 =>
271  Sreg0 <= read_com_S18;
272  rx_data_fifo_rden <= '0';
273  when read_com_S15 =>
274  Sreg0 <= return_st;
275  ram_en <= '0';
276  -- no more accesses from RAM
277  tx_info_fifo_wren <= '0';
278  -- end write to tx info fifo
279  tx_data_fifo_wren <= '0';
280  when read_com_S16 =>
281  if mem_loc_count_reg < q_w_count_reg then
282  Sreg0 <= read_com_S16;
283  ram_addr <= ram_addr_reg;
284  ram_addr_reg <= ram_addr_reg + v_64_1;
285  tx_data_fifo_wren <= '1';
286  mem_loc_count_reg <= mem_loc_count_reg + v_8_1;
287  elsif mem_loc_count_reg >= q_w_count_reg then
288  Sreg0 <= read_com_S15;
289  --ram_en <= '0';
290  -- no more accesses from RAM
291  mem_loc_count_reg <= v_8_0;
292  -- reset the memory location counter
293  ram_addr <= ram_addr_reg;
294  -- Reconsider the CRC error handling
295  if (crc_err = '0') then
296  tx_data_fifo_wren <= '1';
297  else
298  tx_data_fifo_wren <= '0';
299  end if;
300  -- stop writing to the tx data fifo
301  -- need to write code to
302  -- tx_info_fifo
303  tx_info_fifo_wr_data(15 downto 8) <= q_w_count_reg;
304  tx_info_fifo_wr_data(7 downto 0) <= v_8_0;
305  -- This is a read command being responded to
306  tx_info_fifo_wren <= '1';
307  -- write to tx info fifo
308  -- definition of bits written to tx_info_fifo
309  -- bits 15-8: quad word count (read data)
310  -- bits 7-3: status (currently undefined)
311  -- bits 2-0: return code (always 000 from this block)
312  end if;
313  when read_com_S1 =>
314  if q_w_count_reg = v_5_0 then
315  Sreg0 <= read_com_S15;
316  tx_info_fifo_wr_data(15 downto 8) <= q_w_count_reg;
317  tx_info_fifo_wr_data(7 downto 0) <= "00000" & "000";
318  tx_info_fifo_wren <= '1';
319  Tx_FIFO_Reset <= '0';
320  burst_complete_flag <= '0';
321  elsif q_w_count_reg /= v_5_0 then
322  Sreg0 <= read_com_S14;
323  -- there is at least one quad word in the data fifo
324  rx_data_fifo_rden <= '1';
325  Tx_FIFO_Reset <= '0';
326  burst_complete_flag <= '0';
327  end if;
328  when read_com_S18 =>
329  Sreg0 <= read_com_S13;
330  ram_addr_reg <= rx_data_fifo_rd_data;
331  -- obtain starting address
332  when burst_strt_S30 =>
333  Sreg0 <= burst_strt_S34;
334  ram_addr_reg <= rx_data_fifo_rd_data;
335  -- obtain starting address
336  when burst_strt_S31 =>
337  Sreg0 <= burst_strt_S30;
338  rx_data_fifo_rden <= '0';
339  when burst_strt_S33 =>
340  Sreg0 <= burst_strt_S31;
341  -- there is at least one quad word in the data fifo
342  rx_data_fifo_rden <= '1';
343  Tx_FIFO_Reset <= '0';
344  burst_complete_flag <= '0';
345  when burst_strt_S34 =>
346  Sreg0 <= return_st;
347  ram_addr <= ram_addr_reg;
348  burst_start <= '0';
349  when write_com_S9 =>
350  Sreg0 <= write_com_S10;
351  ram_addr <= ram_addr_reg;
352  -- starting address to RAM
353  -- is asserted
354  --ram_addr_reg <= ram_addr_reg + v_64_1;
355  -- prepare the next address
356  mem_loc_count_reg <= mem_loc_count_reg + v_8_1;
357  rx_data_fifo_rden <= '1';
358  -- set up the first word
359  when write_com_S8 =>
360  Sreg0 <= write_com_S19;
361  rx_data_fifo_rden <= '0';
362  when write_com_S10 =>
363  if mem_loc_count_reg = q_w_count_reg then
364  Sreg0 <= write_com_S11;
365  mem_loc_count_reg <= v_8_0;
366  -- Turn off read accesses of the
367  -- data FIFO
368  rx_data_fifo_rden <= '0';
369  ram_addr <= ram_addr_reg;
370  ram_wren <= '1';
371  ram_en <= '1';
372  elsif mem_loc_count_reg < q_w_count_reg then
373  Sreg0 <= write_com_S10;
374  ram_wren <= '1';
375  ram_en <= '1';
376  ram_addr <= ram_addr_reg;
377  ram_addr_reg <= ram_addr_reg + v_64_1;
378  rx_data_fifo_rden <= '1';
379  mem_loc_count_reg <= mem_loc_count_reg + v_8_1;
380  end if;
381  when write_com_S19 =>
382  Sreg0 <= write_com_S9;
383  --rx_data_fifo_rden <= '0';
384  ram_addr_reg <= rx_data_fifo_rd_data;
385  -- starting address from FIFO data
386  -- is latched
387  when write_com_S11 =>
388  Sreg0 <= write_com_S21;
389  ram_wren <= '0';
390  ram_en <= '0';
391  when write_com_S21 =>
392  Sreg0 <= return_st;
393  when crcerr_S24 =>
394  Sreg0 <= return_st;
395  when crcerr_S25 =>
396  Sreg0 <= crcerr_S28;
397  mem_loc_count_reg <= mem_loc_count_reg + v_8_1;
398  rx_data_fifo_rden <= '1';
399  when crcerr_S26 =>
400  Sreg0 <= crcerr_S25;
401  rx_data_fifo_rden <= '0';
402  when crcerr_S27 =>
403  Sreg0 <= crcerr_S24;
404  ram_wren <= '0';
405  ram_en <= '0';
406  when crcerr_S28 =>
407  if mem_loc_count_reg < q_w_count_reg then
408  Sreg0 <= crcerr_S28;
409  mem_loc_count_reg <= mem_loc_count_reg + v_8_1;
410  elsif mem_loc_count_reg = q_w_count_reg then
411  Sreg0 <= crcerr_S27;
412  mem_loc_count_reg <= v_8_0;
413  rx_data_fifo_rden <= '0';
414  end if;
415 --vhdl_cover_off
416  when others =>
417  null;
418 --vhdl_cover_on
419  end case;
420  end if;
421  end if;
422 end process;
423 
424 end RAM_COMM_DEC_9;