otsdaq_prepmodernization  v2_05_00
INFO_FIFO64_0.vhd
1 --------------------------------------------------------------------------------
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28 --------------------------------------------------------------------------------
29 -- You must compile the wrapper file INFO_FIFO64_0.vhd when simulating
30 -- the core, INFO_FIFO64_0. When compiling the wrapper file, be sure to
31 -- reference the XilinxCoreLib VHDL simulation library. For detailed
32 -- instructions, please refer to the "CORE Generator Help".
33 
34 -- The synthesis directives "translate_off/translate_on" specified
35 -- below are supported by Xilinx, Mentor Graphics and Synplicity
36 -- synthesis tools. Ensure they are correct for your synthesis tool(s).
37 
38 LIBRARY ieee;
39 USE ieee.std_logic_1164.ALL;
40 -- synthesis translate_off
41 Library XilinxCoreLib;
42 -- synthesis translate_on
43 ENTITY INFO_FIFO64_0 IS
44  port (
45  clk: IN std_logic;
46  din: IN std_logic_VECTOR(63 downto 0);
47  rd_en: IN std_logic;
48  srst: IN std_logic;
49  wr_en: IN std_logic;
50  dout: OUT std_logic_VECTOR(63 downto 0);
51  empty: OUT std_logic;
52  full: OUT std_logic);
53 END INFO_FIFO64_0;
54 
55 ARCHITECTURE INFO_FIFO64_0_a OF INFO_FIFO64_0 IS
56 -- synthesis translate_off
57 component wrapped_INFO_FIFO64_0
58  port (
59  clk: IN std_logic;
60  din: IN std_logic_VECTOR(63 downto 0);
61  rd_en: IN std_logic;
62  srst: IN std_logic;
63  wr_en: IN std_logic;
64  dout: OUT std_logic_VECTOR(63 downto 0);
65  empty: OUT std_logic;
66  full: OUT std_logic);
67 end component;
68 
69 -- Configuration specification
70  for all : wrapped_INFO_FIFO64_0 use entity XilinxCoreLib.fifo_generator_v4_2(behavioral)
71  generic map(
72  c_has_int_clk => 0,
73  c_rd_freq => 1,
74  c_wr_response_latency => 1,
75  c_has_srst => 1,
76  c_has_rd_data_count => 0,
77  c_din_width => 64,
78  c_has_wr_data_count => 0,
79  c_full_flags_rst_val => 0,
80  c_implementation_type => 0,
81  c_family => "virtex4",
82  c_use_embedded_reg => 0,
83  c_has_wr_rst => 0,
84  c_wr_freq => 1,
85  c_use_dout_rst => 1,
86  c_underflow_low => 0,
87  c_has_meminit_file => 0,
88  c_has_overflow => 0,
89  c_preload_latency => 1,
90  c_dout_width => 64,
91  c_rd_depth => 32,
92  c_default_value => "BlankString",
93  c_mif_file_name => "BlankString",
94  c_has_underflow => 0,
95  c_has_rd_rst => 0,
96  c_has_almost_full => 0,
97  c_has_rst => 0,
98  c_data_count_width => 5,
99  c_has_wr_ack => 0,
100  c_use_ecc => 0,
101  c_wr_ack_low => 0,
102  c_common_clock => 1,
103  c_rd_pntr_width => 5,
104  c_use_fwft_data_count => 0,
105  c_has_almost_empty => 0,
106  c_rd_data_count_width => 5,
107  c_enable_rlocs => 0,
108  c_wr_pntr_width => 5,
109  c_overflow_low => 0,
110  c_prog_empty_type => 0,
111  c_optimization_mode => 0,
112  c_wr_data_count_width => 5,
113  c_preload_regs => 0,
114  c_dout_rst_val => "0",
115  c_has_data_count => 0,
116  c_prog_full_thresh_negate_val => 29,
117  c_wr_depth => 32,
118  c_prog_empty_thresh_negate_val => 3,
119  c_prog_empty_thresh_assert_val => 2,
120  c_has_valid => 0,
121  c_init_wr_pntr_val => 0,
122  c_prog_full_thresh_assert_val => 30,
123  c_use_fifo16_flags => 0,
124  c_has_backup => 0,
125  c_valid_low => 0,
126  c_prim_fifo_type => "512x72",
127  c_count_type => 0,
128  c_prog_full_type => 0,
129  c_memory_type => 1);
130 -- synthesis translate_on
131 BEGIN
132 -- synthesis translate_off
133 U0 : wrapped_INFO_FIFO64_0
134  port map (
135  clk => clk,
136  din => din,
137  rd_en => rd_en,
138  srst => srst,
139  wr_en => wr_en,
140  dout => dout,
141  empty => empty,
142  full => full);
143 -- synthesis translate_on
144 
145 END INFO_FIFO64_0_a;
146