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GEC_RX_CTL_2.vhd
1
-------------------------------------------------------------------------------
2
--
3
-- Title : GEC_RX_CTL_2
4
-- Design : CAPTAN
5
-- Author : aprosser
6
-- Company : CD_CEPA_ESE
7
--
8
-------------------------------------------------------------------------------
9
--
10
-- File : u:\CAPTAN\Data_Conversion_Board\CAPTAN\CAPTAN\compile\GEC_RX_CTL_2.vhd
11
-- Generated : 07/16/08 14:56:37
12
-- From : u:/CAPTAN/Data_Conversion_Board/CAPTAN/CAPTAN/src/GEC_RX_CTL_2.asf
13
-- By : FSM2VHDL ver. 5.0.0.9
14
--
15
-------------------------------------------------------------------------------
16
--
17
-- Description :
18
--
19
-------------------------------------------------------------------------------
20
21
library
IEEE
;
22
use
IEEE.std_logic_1164.
all
;
23
use
IEEE.std_logic_arith.
all
;
24
use
IEEE.std_logic_unsigned.
all
;
25
use
params_package.all
;
26
27
entity
gec_rx_ctl_2
is
28
port
(
29
block_en
:
in
STD_LOGIC
;
30
clock
:
in
STD_LOGIC
;
31
data_fifo_full
:
in
STD_LOGIC
;
32
data_fifo_wrerr
:
in
STD_LOGIC
;
33
gec_user_crc_err
:
in
STD_LOGIC
;
34
gec_user_rx_data_out
:
in
STD_LOGIC_VECTOR
(
7
downto
0
)
;
35
gec_user_rx_size_out
:
in
STD_LOGIC_VECTOR
(
10
downto
0
)
;
36
gec_user_rx_valid_out
:
in
STD_LOGIC
;
37
reset_n
:
in
STD_LOGIC
;
38
crc_err_flag
:
out
STD_LOGIC
;
39
data_fifo_q_w_data
:
out
STD_LOGIC_VECTOR
(
63
downto
0
)
;
40
data_fifo_wren
:
out
STD_LOGIC
;
41
info_fifo_wr_data
:
out
STD_LOGIC_VECTOR
(
15
downto
0
)
;
42
info_fifo_wren
:
out
STD_LOGIC
)
;
43
end
gec_rx_ctl_2
;
44
45
architecture
gec_rx_ctl_2
of
GEC_RX_CTL_2 is
46
47
-- diagram signals declarations
48
signal
com_code
:
STD_LOGIC_VECTOR
(
2
downto
0
)
;
49
signal
crc_err_reg
:
STD_LOGIC
;
50
signal
crc_loop_count
:
STD_LOGIC_VECTOR
(
4
downto
0
)
;
51
signal
q_w_count
:
STD_LOGIC_VECTOR
(
4
downto
0
)
;
52
signal
q_w_counter
:
STD_LOGIC_VECTOR
(
4
downto
0
)
;
53
signal
q_w_reg
:
STD_LOGIC_VECTOR
(
63
downto
0
)
;
54
55
-- SYMBOLIC ENCODED state machine: Sreg0
56
type
Sreg0_type
is
(
57
idle
,
enabled
,
rcvdone
,
S1
,
check_crc
,
S2
,
S3_S4
,
S3_S7
,
S3_S8
,
S3_S9
,
S3_S10
,
S3_S11
,
S3_S12
,
S3_S6
,
S3_S5
58
)
;
59
-- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding
60
61
signal
Sreg0
:
Sreg0_type
;
62
63
begin
64
65
66
----------------------------------------------------------------------
67
-- Machine: Sreg0
68
----------------------------------------------------------------------
69
Sreg0_machine:
process
(clock)
70
begin
71
if
clock
'
event
and
clock
=
'
1
'
then
72
if
reset_n
=
'
0
'
then
73
Sreg0
<=
idle
;
74
-- Set default values for outputs, signals and variables
75
-- ...
76
-- Initialize registers
77
--rx_data_count <= v_5_0;
78
--first_qw <= '0';
79
crc_err_reg
<=
'
0
'
;
80
crc_loop_count
<=
v_5_0
;
81
--q_w_byte_count <= v_3_0;
82
q_w_reg
<=
v_32_0
&
v_32_0
;
83
-- Initialize error flag outputs
84
crc_err_flag
<=
'
0
'
;
85
-- Initialize FIFO control outputs
86
data_fifo_wren
<=
'
0
'
;
87
info_fifo_wren
<=
'
0
'
;
88
info_fifo_wr_data
<=
v_16_0
;
89
com_code
<=
"000"
;
90
else
91
-- Set default values for outputs, signals and variables
92
-- ...
93
case
Sreg0
is
94
when
idle
=
>
95
if
block_en
=
'
0
'
then
96
Sreg0
<=
idle
;
97
elsif
block_en
=
'
1
'
then
98
Sreg0
<=
enabled
;
99
end
if
;
100
when
enabled
=
>
101
if
gec_user_rx_valid_out
=
'
1
'
and
102
block_en
=
'
1
'
and
103
gec_user_rx_size_out
>
v_11_1
then
104
Sreg0
<=
S3_S4
;
105
info_fifo_wr_data
(
7
downto
0
)
<=
gec_user_rx_data_out
;
106
-- Put the entire command/size word in the info
107
-- FIFO
108
-- this is not written until
109
-- all info for the fifo is
110
-- accumulated
111
q_w_count
<=
gec_user_rx_data_out
(
7
downto
3
)
;
112
-- set the terminal count of quad words
113
-- using that portion of the command/size
114
-- word
115
com_code
<=
gec_user_rx_data_out
(
2
downto
0
)
;
116
-- save command code
117
elsif
gec_user_rx_valid_out
=
'
0
'
and
118
block_en
=
'
1
'
then
119
Sreg0
<=
enabled
;
120
elsif
block_en
=
'
0
'
then
121
Sreg0
<=
idle
;
122
elsif
gec_user_rx_valid_out
=
'
1
'
and
123
block_en
=
'
1
'
and
124
gec_user_rx_size_out
=
v_11_1
then
125
Sreg0
<=
check_crc
;
126
info_fifo_wr_data
(
7
downto
0
)
<=
gec_user_rx_data_out
;
127
-- Capture command byte
128
end
if
;
129
when
rcvdone
=
>
130
if
block_en
=
'
0
'
then
131
Sreg0
<=
idle
;
132
info_fifo_wren
<=
'
0
'
;
133
elsif
block_en
=
'
1
'
then
134
Sreg0
<=
enabled
;
135
info_fifo_wren
<=
'
0
'
;
136
end
if
;
137
when
S1
=
>
138
Sreg0
<=
S2
;
139
info_fifo_wr_data
(
13
)
<=
crc_err_reg
;
140
-- keep the crc error status
141
-- at this point the info should be complete
142
crc_err_flag
<=
crc_err_reg
;
143
-- assert the crc error status on the output
144
when
check_crc
=
>
145
if
(
crc_loop_count
=
v_5_22
)
or
146
(
gec_user_crc_err
=
'
1
'
)
or
147
(
crc_err_reg
=
'
1
'
)
then
-- CRC timed out -- or CRC err detected
148
Sreg0
<=
S1
;
149
if
(
gec_user_crc_err
=
'
1
'
)
then
150
crc_err_reg
<=
'
1
'
;
151
end
if
;
152
--info_fifo_wr_data(12 downto 8) <= rx_data_count;
153
-- rx_data_count is the number of quad words received
154
elsif
(
crc_loop_count
<
v_5_22
)
and
155
(
gec_user_crc_err
=
'
0
'
)
then
-- waiting for CRC time out
156
Sreg0
<=
check_crc
;
157
crc_loop_count
<=
crc_loop_count
+
v_5_1
;
158
end
if
;
159
when
S2
=
>
160
Sreg0
<=
rcvdone
;
161
--rx_data_count <= v_5_0;
162
-- reset the quad word counter
163
crc_err_reg
<=
'
0
'
;
164
-- reset the crc error counter
165
crc_err_flag
<=
'
0
'
;
166
-- reset the crc error flag (output)
167
crc_loop_count
<=
v_5_0
;
168
-- reset the 22 cycle crc loop counter
169
data_fifo_wren
<=
'
0
'
;
170
info_fifo_wren
<=
'
1
'
;
171
-- we actually write the info fifo here.
172
--first_qw <= '0';
173
-- reset first quad word indicator
174
when
S3_S4
=
>
175
Sreg0
<=
S3_S5
;
176
data_fifo_q_w_data
(
63
downto
56
)
<=
gec_user_rx_data_out
;
177
q_w_counter
<=
v_5_1
;
178
-- initialize the counter
179
case
com_code
is
180
when
"000"
=
>
181
-- read
182
q_w_count
<=
v_5_1
;
183
-- Increment the quad word count for writes
184
-- First word is the starting address
185
-- next n words (I received a count of n)
186
-- is the actual quad word data for writing.
187
-- This will cause only the address word
188
-- to be written to the data fifo.
189
when
"001"
=
>
190
-- write
191
q_w_count
<=
q_w_count
+
v_5_1
;
192
-- watch out for overflow
193
-- writes the starting address first plus the
194
-- data
195
when
"010"
=
>
196
-- read
197
q_w_count
<=
v_5_1
;
198
-- This will cause only the address word
199
-- to be written to the data fifo.
200
when
"011"
=
>
201
-- read
202
q_w_count
<=
v_5_1
;
203
-- This will cause only the address word
204
-- to be written to the data fifo.
205
when
others
=
>
206
q_w_count
<=
v_5_1
;
207
end
case
;
208
when
S3_S7
=
>
209
Sreg0
<=
S3_S8
;
210
data_fifo_q_w_data
(
39
downto
32
)
<=
gec_user_rx_data_out
;
211
when
S3_S8
=
>
212
Sreg0
<=
S3_S9
;
213
data_fifo_q_w_data
(
31
downto
24
)
<=
gec_user_rx_data_out
;
214
when
S3_S9
=
>
215
Sreg0
<=
S3_S10
;
216
data_fifo_q_w_data
(
23
downto
16
)
<=
gec_user_rx_data_out
;
217
when
S3_S10
=
>
218
Sreg0
<=
S3_S11
;
219
data_fifo_q_w_data
(
15
downto
8
)
<=
gec_user_rx_data_out
;
220
when
S3_S11
=
>
221
Sreg0
<=
S3_S12
;
222
data_fifo_wren
<=
'
1
'
;
223
-- write the assembled data to the FIFO
224
data_fifo_q_w_data
(
7
downto
0
)
<=
gec_user_rx_data_out
;
225
when
S3_S12
=
>
226
if
q_w_counter
<
q_w_count
then
227
Sreg0
<=
S3_S5
;
228
data_fifo_q_w_data
(
63
downto
56
)
<=
gec_user_rx_data_out
;
229
data_fifo_wren
<=
'
0
'
;
230
-- Finish the write to the data fifo
231
q_w_counter
<=
q_w_counter
+
v_5_1
;
232
-- increment the counter
233
elsif
q_w_counter
=
q_w_count
then
234
Sreg0
<=
check_crc
;
235
data_fifo_wren
<=
'
0
'
;
236
-- finish data FIFO write
237
if
(
gec_user_crc_err
=
'
1
'
)
then
238
crc_err_reg
<=
'
1
'
;
239
end
if
;
240
crc_loop_count
<=
crc_loop_count
+
v_5_1
;
241
-- increment loop counter for catching CRC errors
242
end
if
;
243
when
S3_S6
=
>
244
Sreg0
<=
S3_S7
;
245
data_fifo_q_w_data
(
47
downto
40
)
<=
gec_user_rx_data_out
;
246
when
S3_S5
=
>
247
Sreg0
<=
S3_S6
;
248
data_fifo_q_w_data
(
55
downto
48
)
<=
gec_user_rx_data_out
;
249
when
others
=
>
250
null
;
251
end
case
;
252
end
if
;
253
end
if
;
254
end
process
;
255
256
end
GEC_RX_CTL_2
;
gec_rx_ctl_2
Definition:
GEC_RX_CTL_2.vhd:27
src
firmware
g-2
KickerControllerFirmware
GEL_CAPTAN
GEC_RX_CTL_2.vhd
Generated on Wed Oct 2 2019 09:53:12 for otsdaq_prepmodernization by
1.8.5