otsdaq_prepmodernization  v2_04_02
INFO_FIFO_0_exdes.vhd
1 --------------------------------------------------------------------------------
2 --
3 -- FIFO Generator Core - core top file for implementation
4 --
5 --------------------------------------------------------------------------------
6 --
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52 --------------------------------------------------------------------------------
53 --
54 -- Filename: INFO_FIFO_0_exdes.vhd
55 --
56 -- Description:
57 -- This is the FIFO core wrapper with BUFG instances for clock connections.
58 --
59 --------------------------------------------------------------------------------
60 -- Library Declarations
61 --------------------------------------------------------------------------------
62 
63 library ieee;
64 use ieee.std_logic_1164.all;
65 use ieee.std_logic_arith.all;
66 use ieee.std_logic_unsigned.all;
67 
68 library unisim;
69 use unisim.vcomponents.all;
70 
71 --------------------------------------------------------------------------------
72 -- Entity Declaration
73 --------------------------------------------------------------------------------
75  PORT (
76  CLK : IN std_logic;
77  SRST : IN std_logic;
78  WR_EN : IN std_logic;
79  RD_EN : IN std_logic;
80  DIN : IN std_logic_vector(16-1 DOWNTO 0);
81  DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
82  FULL : OUT std_logic;
83  EMPTY : OUT std_logic);
84 
85 end INFO_FIFO_0_exdes;
86 
87 
88 
89 architecture xilinx of INFO_FIFO_0_exdes is
90 
91  signal clk_i : std_logic;
92 
93 
94 
95  component INFO_FIFO_0 is
96  PORT (
97  CLK : IN std_logic;
98  SRST : IN std_logic;
99  WR_EN : IN std_logic;
100  RD_EN : IN std_logic;
101  DIN : IN std_logic_vector(16-1 DOWNTO 0);
102  DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
103  FULL : OUT std_logic;
104  EMPTY : OUT std_logic);
105 
106  end component;
107 
108 
109 begin
110  clk_buf: bufg
111  PORT map(
112  i => CLK,
113  o => clk_i
114  );
115 
116 
117 
118  exdes_inst : INFO_FIFO_0
119  PORT MAP (
120  CLK => clk_i,
121  SRST => srst,
122  WR_EN => wr_en,
123  RD_EN => rd_en,
124  DIN => din,
125  DOUT => dout,
126  FULL => full,
127  EMPTY => empty);
128 
129 end xilinx;