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GEC_RX_CTL_1.vhd
1
-------------------------------------------------------------------------------
2
--
3
-- Title : GEC_RX_CTL_1
4
-- Design : CAPTAN
5
-- Author : aprosser
6
-- Company : CD_CEPA_ESE
7
--
8
-------------------------------------------------------------------------------
9
--
10
-- File : u:\CAPTAN\Data_Conversion_Board\CAPTAN\CAPTAN\compile\GEC_RX_CTL_1.vhd
11
-- Generated : 06/17/08 10:04:53
12
-- From : u:/CAPTAN/Data_Conversion_Board/CAPTAN/CAPTAN/src/GEC_RX_CTL_1.asf
13
-- By : FSM2VHDL ver. 5.0.0.9
14
--
15
-------------------------------------------------------------------------------
16
--
17
-- Description :
18
--
19
-------------------------------------------------------------------------------
20
21
library
IEEE
;
22
use
IEEE.std_logic_1164.
all
;
23
use
IEEE.std_logic_arith.
all
;
24
use
IEEE.std_logic_unsigned.
all
;
25
use
params_package.all
;
26
27
entity
gec_rx_ctl_1
is
28
port
(
29
block_en
:
in
STD_LOGIC
;
30
clock
:
in
STD_LOGIC
;
31
data_fifo_full
:
in
STD_LOGIC
;
32
data_fifo_wrerr
:
in
STD_LOGIC
;
33
gec_user_crc_err
:
in
STD_LOGIC
;
34
gec_user_rx_data_out
:
in
STD_LOGIC_VECTOR
(
7
downto
0
)
;
35
gec_user_rx_size_out
:
in
STD_LOGIC_VECTOR
(
10
downto
0
)
;
36
gec_user_rx_valid_out
:
in
STD_LOGIC
;
37
reset_n
:
in
STD_LOGIC
;
38
crc_err_flag
:
out
STD_LOGIC
;
39
data_fifo_q_w_data
:
out
STD_LOGIC_VECTOR
(
63
downto
0
)
;
40
data_fifo_wren
:
out
STD_LOGIC
;
41
info_fifo_wr_data
:
out
STD_LOGIC_VECTOR
(
15
downto
0
)
;
42
info_fifo_wren
:
out
STD_LOGIC
)
;
43
end
gec_rx_ctl_1
;
44
45
architecture
gec_rx_ctl_1
of
GEC_RX_CTL_1 is
46
47
-- diagram signals declarations
48
signal
crc_err_reg
:
STD_LOGIC
;
49
signal
crc_loop_count
:
STD_LOGIC_VECTOR
(
4
downto
0
)
;
50
signal
first_byte
:
STD_LOGIC
;
51
signal
q_w_byte_count
:
STD_LOGIC_VECTOR
(
2
downto
0
)
;
52
signal
q_w_reg
:
STD_LOGIC_VECTOR
(
63
downto
0
)
;
53
signal
rx_data_count
:
STD_LOGIC_VECTOR
(
4
downto
0
)
;
54
55
-- SYMBOLIC ENCODED state machine: Sreg0
56
type
Sreg0_type
is
(
57
idle
,
enabled
,
data_arrive
,
rcvdone
,
S1
,
update_info
,
S2
58
)
;
59
-- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding
60
61
signal
Sreg0
:
Sreg0_type
;
62
63
begin
64
65
66
----------------------------------------------------------------------
67
-- Machine: Sreg0
68
----------------------------------------------------------------------
69
Sreg0_machine:
process
(clock)
70
begin
71
if
clock
'
event
and
clock
=
'
1
'
then
72
if
reset_n
=
'
0
'
then
73
Sreg0
<=
idle
;
74
-- Set default values for outputs, signals and variables
75
-- ...
76
-- Initialize registers
77
rx_data_count
<=
v_5_0
;
78
first_byte
<=
'
0
'
;
79
crc_err_reg
<=
'
0
'
;
80
crc_loop_count
<=
v_5_0
;
81
q_w_byte_count
<=
v_3_0
;
82
q_w_reg
<=
v_32_0
&
v_32_0
;
83
-- Initialize error flag outputs
84
crc_err_flag
<=
'
0
'
;
85
-- Initialize FIFO control outputs
86
data_fifo_wren
<=
'
0
'
;
87
info_fifo_wren
<=
'
0
'
;
88
info_fifo_wr_data
<=
v_16_0
;
89
else
90
-- Set default values for outputs, signals and variables
91
-- ...
92
case
Sreg0
is
93
when
idle
=
>
94
if
block_en
=
'
0
'
then
95
Sreg0
<=
idle
;
96
elsif
block_en
=
'
1
'
then
97
Sreg0
<=
enabled
;
98
end
if
;
99
when
enabled
=
>
100
if
gec_user_rx_valid_out
=
'
0
'
then
101
Sreg0
<=
enabled
;
102
elsif
gec_user_rx_valid_out
=
'
1
'
then
103
Sreg0
<=
data_arrive
;
104
info_fifo_wr_data
(
7
downto
0
)
<=
gec_user_rx_data_out
;
105
-- Capture command byte
106
--info_fifo_wren <= '1';
107
end
if
;
108
when
data_arrive
=
>
109
if
gec_user_rx_valid_out
=
'
1
'
then
110
Sreg0
<=
data_arrive
;
111
info_fifo_wren
<=
'
0
'
;
112
case
q_w_byte_count
is
113
when
"000"
=
>
114
if
(
first_byte
=
'
0
'
)
then
115
first_byte
<=
'
1
'
;
116
data_fifo_wren
<=
'
0
'
;
117
-- no quad word write strobe
118
else
119
data_fifo_wren
<=
'
1
'
;
120
-- generate a quad word write strobe
121
q_w_byte_count
<=
q_w_byte_count
+
"001"
;
122
-- increment q_w_byte_count
123
end
if
;
124
rx_data_count
<=
rx_data_count
+
v_5_1
;
125
-- increment quad word count
126
q_w_reg
(
7
downto
0
)
<=
gec_user_rx_data_out
;
127
-- write the assemebled quad word data to the FIFO
128
-- increment the count of quad words
129
when
"001"
=
>
130
q_w_byte_count
<=
q_w_byte_count
+
"001"
;
131
-- increment q_w_byte_count
132
data_fifo_wren
<=
'
0
'
;
133
-- no quad word write strobe
134
q_w_reg
(
15
downto
8
)
<=
gec_user_rx_data_out
;
135
when
"010"
=
>
136
q_w_byte_count
<=
q_w_byte_count
+
"001"
;
137
-- increment q_w_byte_count
138
data_fifo_wren
<=
'
0
'
;
139
-- no quad word write strobe
140
q_w_reg
(
23
downto
16
)
<=
gec_user_rx_data_out
;
141
when
"011"
=
>
142
q_w_byte_count
<=
q_w_byte_count
+
"001"
;
143
-- increment q_w_byte_count
144
data_fifo_wren
<=
'
0
'
;
145
-- no quad word write strobe
146
q_w_reg
(
31
downto
24
)
<=
gec_user_rx_data_out
;
147
when
"100"
=
>
148
q_w_byte_count
<=
q_w_byte_count
+
"001"
;
149
-- increment q_w_byte_count
150
data_fifo_wren
<=
'
0
'
;
151
-- no quad word write strobe
152
q_w_reg
(
39
downto
32
)
<=
gec_user_rx_data_out
;
153
when
"101"
=
>
154
q_w_byte_count
<=
q_w_byte_count
+
"001"
;
155
-- increment q_w_byte_count
156
data_fifo_wren
<=
'
0
'
;
157
-- no quad word write strobe
158
q_w_reg
(
47
downto
40
)
<=
gec_user_rx_data_out
;
159
when
"110"
=
>
160
q_w_byte_count
<=
q_w_byte_count
+
"001"
;
161
-- increment q_w_byte_count
162
data_fifo_wren
<=
'
0
'
;
163
-- no quad word write strobe
164
q_w_reg
(
55
downto
48
)
<=
gec_user_rx_data_out
;
165
when
"111"
=
>
166
q_w_byte_count
<=
"000"
;
167
-- reset q_w_byte_count
168
data_fifo_wren
<=
'
0
'
;
169
q_w_reg
(
63
downto
56
)
<=
gec_user_rx_data_out
;
170
when
others
=
>
171
data_fifo_wren
<=
'
0
'
;
172
end
case
;
173
elsif
gec_user_rx_valid_out
=
'
0
'
then
174
Sreg0
<=
update_info
;
175
if
(
gec_user_crc_err
=
'
1
'
)
then
176
crc_err_reg
<=
'
1
'
;
177
end
if
;
178
data_fifo_wren
<=
'
0
'
;
179
info_fifo_wren
<=
'
0
'
;
180
end
if
;
181
when
rcvdone
=
>
182
if
block_en
=
'
0
'
then
183
Sreg0
<=
idle
;
184
elsif
block_en
=
'
1
'
then
185
Sreg0
<=
enabled
;
186
end
if
;
187
when
S1
=
>
188
Sreg0
<=
S2
;
189
info_fifo_wr_data
(
13
)
<=
crc_err_reg
;
190
when
update_info
=
>
191
if
(
crc_loop_count
=
v_5_22
)
or
192
(
gec_user_crc_err
=
'
1
'
)
or
193
(
crc_err_reg
=
'
1
'
)
then
194
Sreg0
<=
S1
;
195
if
(
gec_user_crc_err
=
'
1
'
)
then
196
crc_err_reg
<=
'
1
'
;
197
end
if
;
198
info_fifo_wr_data
(
12
downto
8
)
<=
rx_data_count
;
199
--info_fifo_wren <= '1';
200
elsif
(
crc_loop_count
<
v_5_22
)
and
201
(
gec_user_crc_err
=
'
0
'
)
then
202
Sreg0
<=
update_info
;
203
crc_loop_count
<=
crc_loop_count
+
v_5_1
;
204
end
if
;
205
when
S2
=
>
206
Sreg0
<=
rcvdone
;
207
rx_data_count
<=
v_5_0
;
208
crc_err_reg
<=
'
0
'
;
209
crc_err_flag
<=
'
0
'
;
210
crc_loop_count
<=
v_5_0
;
211
data_fifo_wren
<=
'
0
'
;
212
info_fifo_wren
<=
'
1
'
;
213
info_fifo_wr_data
<=
v_16_0
;
214
when
others
=
>
215
null
;
216
end
case
;
217
end
if
;
218
end
if
;
219
end
process
;
220
221
end
GEC_RX_CTL_1
;
gec_rx_ctl_1
Definition:
GEC_RX_CTL_1.vhd:27
src
firmware
g-2
KickerControllerFirmware
GEL_CAPTAN
GEC_RX_CTL_1.vhd
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