otsdaq_prepmodernization  v2_04_02
ADC_FIFO_synth.vhd
1 --------------------------------------------------------------------------------
2 --
3 -- FIFO Generator Core Demo Testbench
4 --
5 --------------------------------------------------------------------------------
6 --
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8 --
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52 --------------------------------------------------------------------------------
53 --
54 -- Filename: ADC_FIFO_synth.vhd
55 --
56 -- Description:
57 -- This is the demo testbench for fifo_generator core.
58 --
59 --------------------------------------------------------------------------------
60 -- Library Declarations
61 --------------------------------------------------------------------------------
62 
63 
64 LIBRARY ieee;
65 USE ieee.STD_LOGIC_1164.ALL;
66 USE ieee.STD_LOGIC_unsigned.ALL;
67 USE IEEE.STD_LOGIC_arith.ALL;
68 USE ieee.numeric_std.ALL;
69 USE ieee.STD_LOGIC_misc.ALL;
70 
71 LIBRARY std;
72 USE std.textio.ALL;
73 
74 LIBRARY work;
75 USE work.ADC_FIFO_pkg.ALL;
76 
77 --------------------------------------------------------------------------------
78 -- Entity Declaration
79 --------------------------------------------------------------------------------
80 ENTITY ADC_FIFO_synth IS
81  GENERIC(
82  FREEZEON_ERROR : INTEGER := 0;
83  TB_STOP_CNT : INTEGER := 0;
84  TB_SEED : INTEGER := 1
85  );
86  PORT(
87  WR_CLK : IN STD_LOGIC;
88  RD_CLK : IN STD_LOGIC;
89  RESET : IN STD_LOGIC;
90  SIM_DONE : OUT STD_LOGIC;
91  STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
92  );
93 END ENTITY;
94 
95 ARCHITECTURE simulation_arch OF ADC_FIFO_synth IS
96 
97  -- FIFO interface signal declarations
98  SIGNAL wr_clk_i : STD_LOGIC;
99  SIGNAL rd_clk_i : STD_LOGIC;
100  SIGNAL valid : STD_LOGIC;
101  SIGNAL overflow : STD_LOGIC;
102  SIGNAL wr_en : STD_LOGIC;
103  SIGNAL rd_en : STD_LOGIC;
104  SIGNAL din : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
105  SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
106  SIGNAL full : STD_LOGIC;
107  SIGNAL empty : STD_LOGIC;
108  -- TB Signals
109  SIGNAL wr_data : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
110  SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
111  SIGNAL wr_en_i : STD_LOGIC := '0';
112  SIGNAL rd_en_i : STD_LOGIC := '0';
113  SIGNAL full_i : STD_LOGIC := '0';
114  SIGNAL empty_i : STD_LOGIC := '0';
115  SIGNAL almost_full_i : STD_LOGIC := '0';
116  SIGNAL almost_empty_i : STD_LOGIC := '0';
117  SIGNAL prc_we_i : STD_LOGIC := '0';
118  SIGNAL prc_re_i : STD_LOGIC := '0';
119  SIGNAL dout_chk_i : STD_LOGIC := '0';
120  SIGNAL rst_int_rd : STD_LOGIC := '0';
121  SIGNAL rst_int_wr : STD_LOGIC := '0';
122  SIGNAL rst_s_wr1 : STD_LOGIC := '0';
123  SIGNAL rst_s_wr2 : STD_LOGIC := '0';
124  SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
125  SIGNAL rst_s_wr3 : STD_LOGIC := '0';
126  SIGNAL rst_s_rd : STD_LOGIC := '0';
127  SIGNAL reset_en : STD_LOGIC := '0';
128  SIGNAL rst_async_wr1 : STD_LOGIC := '0';
129  SIGNAL rst_async_wr2 : STD_LOGIC := '0';
130  SIGNAL rst_async_wr3 : STD_LOGIC := '0';
131  SIGNAL rst_async_rd1 : STD_LOGIC := '0';
132  SIGNAL rst_async_rd2 : STD_LOGIC := '0';
133  SIGNAL rst_async_rd3 : STD_LOGIC := '0';
134 
135 
136  BEGIN
137 
138  ---- Reset generation logic -----
139  rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
140  rst_int_rd <= rst_async_rd3 OR rst_s_rd;
141 
142  --Testbench reset synchronization
143  PROCESS(rd_clk_i,RESET)
144  BEGIN
145  IF(RESET = '1') THEN
146  rst_async_rd1 <= '1';
147  rst_async_rd2 <= '1';
148  rst_async_rd3 <= '1';
149  ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
150  rst_async_rd1 <= RESET;
151  rst_async_rd2 <= rst_async_rd1;
152  rst_async_rd3 <= rst_async_rd2;
153  END IF;
154  END PROCESS;
155 
156  PROCESS(wr_clk_i,RESET)
157  BEGIN
158  IF(RESET = '1') THEN
159  rst_async_wr1 <= '1';
160  rst_async_wr2 <= '1';
161  rst_async_wr3 <= '1';
162  ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
163  rst_async_wr1 <= RESET;
164  rst_async_wr2 <= rst_async_wr1;
165  rst_async_wr3 <= rst_async_wr2;
166  END IF;
167  END PROCESS;
168  rst_s_wr3 <= '0';
169  rst_s_rd <= '0';
170  ------------------
171 
172  ---- Clock buffers for testbench ----
173  wr_clk_i <= WR_CLK;
174  rd_clk_i <= RD_CLK;
175  ------------------
176 
177  din <= wr_data;
178  dout_i <= dout;
179  wr_en <= wr_en_i;
180  rd_en <= rd_en_i;
181  full_i <= full;
182  empty_i <= empty;
183 
184  fg_dg_nv: ADC_FIFO_dgen
185  GENERIC MAP (
186  C_DIN_WIDTH => 16,
187  C_DOUT_WIDTH => 64,
188  TB_SEED => TB_SEED ,
189  C_CH_TYPE => 0
190  )
191  PORT MAP ( -- Write Port
192  RESET => rst_int_wr,
193  WR_CLK => wr_clk_i,
194  PRC_WR_EN => prc_we_i,
195  FULL => full_i,
196  WR_EN => wr_en_i,
197  WR_DATA => wr_data
198  );
199 
200  fg_dv_nv: ADC_FIFO_dverif
201  GENERIC MAP (
202  C_DOUT_WIDTH => 64,
203  C_DIN_WIDTH => 16,
204  C_USE_EMBEDDED_REG => 0,
205  TB_SEED => TB_SEED,
206  C_CH_TYPE => 0
207  )
208  PORT MAP(
209  RESET => rst_int_rd,
210  RD_CLK => rd_clk_i,
211  PRC_RD_EN => prc_re_i,
212  RD_EN => rd_en_i,
213  EMPTY => empty_i,
214  DATA_OUT => dout_i,
215  DOUT_CHK => dout_chk_i
216  );
217 
218  fg_pc_nv: ADC_FIFO_pctrl
219  GENERIC MAP (
220  AXI_CHANNEL => "Native",
221  C_APPLICATION_TYPE => 0,
222  C_DOUT_WIDTH => 64,
223  C_DIN_WIDTH => 16,
224  C_WR_PNTR_WIDTH => 6,
225  C_RD_PNTR_WIDTH => 4,
226  C_CH_TYPE => 0,
227  FREEZEON_ERROR => FREEZEON_ERROR ,
228  TB_SEED => TB_SEED,
229  TB_STOP_CNT => TB_STOP_CNT
230  )
231  PORT MAP(
232  RESET_WR => rst_int_wr,
233  RESET_RD => rst_int_rd,
234  RESET_EN => reset_en,
235  WR_CLK => wr_clk_i,
236  RD_CLK => rd_clk_i,
237  PRC_WR_EN => prc_we_i,
238  PRC_RD_EN => prc_re_i,
239  FULL => full_i,
240  ALMOST_FULL => almost_full_i ,
241  ALMOST_EMPTY => almost_empty_i ,
242  DOUT_CHK => dout_chk_i,
243  EMPTY => empty_i,
244  DATA_IN => wr_data,
245  DATA_OUT => dout,
246  SIM_DONE => SIM_DONE,
247  STATUS => STATUS
248  );
249 
250 
251 
252 
253 
254  ADC_FIFO_inst : ADC_FIFO_exdes
255  PORT MAP (
256  WR_CLK => wr_clk_i,
257  RD_CLK => rd_clk_i,
258  VALID => valid,
259  OVERFLOW => overflow,
260  WR_EN => wr_en,
261  RD_EN => rd_en,
262  DIN => din,
263  DOUT => dout,
264  FULL => full,
265  EMPTY => empty);
266 
267 END ARCHITECTURE;