otsdaq_prepmodernization  v2_04_02
TOP_LEVEL.vhd
1 library ieee;
2 use ieee.std_logic_1164.ALL;
3 use ieee.numeric_std.ALL;
4 use ieee.std_logic_misc.ALL;
5 
6 library UNISIM;
7 use UNISIM.Vcomponents.ALL;
8 
9 
10 entity top is
11  port (
12  PHY_RXCLK : in std_logic;
13  PHY_RXCTL_RXDV : in std_logic;
14  PHY_RXD0 : in std_logic;
15  PHY_RXD1 : in std_logic;
16  PHY_RXD2 : in std_logic;
17  PHY_RXD3 : in std_logic;
18  PHY_RXD4 : in std_logic;
19  PHY_RXD5 : in std_logic;
20  PHY_RXD6 : in std_logic;
21  PHY_RXD7 : in std_logic;
22 
23  --PHY_RXER : in std_logic;
24  --USER_CLOCK : in std_logic;
25 
26  --PHY_RESET : out std_logic;
27 
28  PHY_TXCTL_TXEN : out std_logic;
29  PHY_TXD0 : out std_logic;
30  PHY_TXD1 : out std_logic;
31  PHY_TXD2 : out std_logic;
32  PHY_TXD3 : out std_logic;
33  PHY_TXD4 : out std_logic;
34  PHY_TXD5 : out std_logic;
35  PHY_TXD6 : out std_logic;
36  PHY_TXD7 : out std_logic;
37  PHY_TXER : out std_logic;
38 
39  PHY_TXC_GTXCLK : out std_logic
40 
41 
42  );
43 end top;
44 
45 architecture BEHAVIORAL of top is
46 
47 
48  attribute BOX_TYPE : string ;
49  attribute IOSTANDARD : string ;
50  attribute CAPACITANCE : string ;
51  attribute SLEW : string ;
52  attribute DRIVE : string ;
53  attribute IBUF_LOW_PWR : string ;
54 
55  signal b_data : std_logic_vector (63 downto 0);
56  signal b_data_we : std_logic;
57  signal GMII_RXD_0_sig : std_logic_vector (7 downto 0);
58  signal GMII_RX_DV_0_sig : std_logic;
59  signal GMII_RX_ER_0_sig : std_logic;
60  signal GTX_CLK_0_sig : std_logic;
61  signal MASTER_CLK : std_logic;
62  signal CLK15NS, CLK15NS_sig : std_logic;
63 
64  signal gec_mac, gec_user_src_mac : std_logic_vector (47 downto 0);
65  signal gec_port, gec_user_src_port : std_logic_vector (15 downto 0);
66  signal gec_addrs, gec_user_src_addrs : std_logic_vector (7 downto 0);
67 
68  signal gec_user_src_capture : std_logic;
69 
70  signal reset_btn : std_logic;
71  signal gnd : std_logic;
72 
73 
74  signal PHY_TXD_sig : std_logic_vector (7 downto 0);
75  signal PHY_TXEN_sig : std_logic;
76  signal PHY_TXER_sig : std_logic;
77  signal psi_status : std_logic_vector (63 downto 0);
78  signal reset : std_logic;
79  signal reset_n : std_logic;
80  signal rx_addr : std_logic_vector (31 downto 0);
81  signal rx_data : std_logic_vector (63 downto 0);
82  signal rx_wren : std_logic;
83  signal secondary_clk, secondary_clk_sig : std_logic;
84  signal tx_data : std_logic_vector (63 downto 0);
85 
86 
87 
88 
89  attribute mark_debug : string;
90  attribute mark_debug of MASTER_CLK : signal is "true";
91  attribute mark_debug of secondary_clk : signal is "true";
92  attribute mark_debug of PHY_TXD_sig : signal is "true";
93  attribute mark_debug of PHY_TXEN_sig : signal is "true";
94  attribute mark_debug of rx_wren : signal is "true";
95  attribute mark_debug of CLK15NS : signal is "true";
96 
97  -- attribute mark_debug of GMII_RXD_0_sig : signal is "true";
98  -- attribute mark_debug of GMII_RX_DV_0_sig : signal is "true";
99  -- attribute mark_debug of rx_addr : signal is "true";
100  -- attribute mark_debug of rx_data : signal is "true";
101 
102 
103 
104  component OBUF
105  port ( I : in std_logic;
106  O : out std_logic);
107  end component;
108  attribute IOSTANDARD of OBUF : component is "DEFAULT";
109  attribute CAPACITANCE of OBUF : component is "DONT_CARE";
110  attribute SLEW of OBUF : component is "SLOW";
111  attribute DRIVE of OBUF : component is "12";
112  attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
113 
114  component IBUF
115  port ( I : in std_logic;
116  O : out std_logic);
117  end component;
118  attribute IOSTANDARD of IBUF : component is "DEFAULT";
119  attribute CAPACITANCE of IBUF : component is "DONT_CARE";
120  attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
121 
122  component IBUFG
123  -- synopsys translate_off
124  generic( IBUF_LOW_PWR : boolean := TRUE);
125  -- synopsys translate_on
126  port ( I : in std_logic;
127  O : out std_logic);
128  end component;
129  attribute IOSTANDARD of IBUFG : component is "DEFAULT";
130  attribute CAPACITANCE of IBUFG : component is "DONT_CARE";
131  attribute IBUF_LOW_PWR of IBUFG : component is "TRUE";
132  attribute BOX_TYPE of IBUFG : component is "BLACK_BOX";
133 
134 
135  component BUFG
136  port ( I : in std_logic;
137  O : out std_logic);
138  end component;
139  attribute BOX_TYPE of BUFG : component is "BLACK_BOX";
140 
141  component reset_mgr
142  port ( slow_clk : in std_logic;
143  reset_start : in std_logic;
144  reset : out std_logic);
145  end component;
146 
147 
148 
149 begin
150 
151  gnd <= '0';
152 
153  reset_n <= not reset;
154  reset_btn <= '0';
155 
156  -- reset_ibuf : IBUF -- SW3 on board is active high
157  -- port map (I=>GPIO_SW_W, O=>reset_btn);
158  -- user_led1: OBUF -- LED display of RESET
159  -- port map (I=>reset, O=>PZ_ULED_1);
160 
161 
162  -- start simple OEI
163  eth_interface : entity work.Ethernet_Interface
164  port map (b_data(63 downto 0)=>b_data(63 downto 0),
165  b_data_we =>b_data_we,
166  PHY_RXD(7 downto 0)=>GMII_RXD_0_sig(7 downto 0),
167  PHY_RX_DV =>GMII_RX_DV_0_sig,
168  PHY_RX_ER =>GMII_RX_ER_0_sig,
169  MASTER_CLK =>MASTER_CLK,
170  reset_in =>reset_btn,
171  reset_out => reset,
172  tx_data(63 downto 0)=>tx_data(63 downto 0),
173  b_enable =>open,
174  TX_CLK =>GTX_CLK_0_sig,
175  PHY_TXD(7 downto 0)=>PHY_TXD_sig(7 downto 0),
176  PHY_TX_EN =>PHY_TXEN_sig,
177  PHY_TX_ER =>PHY_TXER_sig,
178  rx_addr(31 downto 0)=>rx_addr(31 downto 0),
179  rx_data(63 downto 0)=>rx_data(63 downto 0),
180  rx_wren =>rx_wren);
181 
182  -- end simple OEI
183 
184 
185 
186 
187 
188  -- start data gen block
189  dataGenGen : for i in 0 to 0 generate
190  signal reg_cnt : unsigned(63 downto 0) := (others => '0'); -- 1s is infinite
191  signal reg_rate : unsigned(63 downto 0) := (others => '0'); -- delay between 8 clock periods
192 
193  signal cnt : unsigned(2 downto 0) := (others => '0');
194  signal delay_cnt : unsigned(63 downto 0) := (others => '0');
195  signal data_cnt : unsigned(31 downto 0) := (others => '0');
196  begin
197  process(MASTER_CLK)
198  begin
199  if (rising_edge(MASTER_CLK)) then
200 
201  b_data_we <= '0';
202 
203  -- register map
204  if (rx_wren = '1') then
205  if (unsigned(rx_addr) = x"1001") then --reg_cnt
206  reg_cnt <= unsigned(rx_data);
207  elsif (unsigned(rx_addr) = x"1002") then --reg_rate
208  reg_rate <= unsigned(rx_data);
209  end if;
210  delay_cnt <= (others => '0'); --reset delay and execute burst write
211  end if;
212 
213  cnt <= cnt + 1;
214  if (cnt = 0) then --count groups of 8 with wrap around
215  delay_cnt <= delay_cnt + 1;
216 
217  if (delay_cnt = reg_rate and reg_cnt /= 0) then
218  delay_cnt <= (others => '0'); --reset delay and execute burst write
219  b_data(63 downto 32) <= std_logic_vector(data_cnt);
220  b_data(31 downto 0) <= tx_data(31 downto 0); -- last saved write
221  b_data_we <= '1';
222  data_cnt <= data_cnt + 1;
223 
224  if ( and_reduce(std_logic_vector(reg_cnt)) /= '1' ) then --count down pulses, if not infinite
225  reg_cnt <= reg_cnt - 1;
226  end if;
227  end if;
228  end if;
229  end if;
230 
231  end process;
232  end generate;
233 
234  -- end data gen block
235 
236 
237  makeSlowClock : for i in 0 to 0 generate
238  signal cnt : unsigned(4 downto 0) := (others => '0');
239  begin
240  secondary_clk_sig <= cnt(4); -- 32 times slower clock than MASTER_CLK
241  CLK15NS_sig <= cnt(0); -- 2 times slower clock than MASTER_CLK
242  process(MASTER_CLK)
243  begin
244  if (rising_edge(MASTER_CLK)) then
245  cnt <= cnt + 1;
246  end if;
247  end process;
248  end generate;
249 
250  CLK5MHz_bufg : BUFG
251  port map (I =>secondary_clk_sig, O =>secondary_clk);
252 
253  CLK15NS_bufg : BUFG
254  port map (I =>CLK15NS_sig, O =>CLK15NS );
255 
256  -- tx_data for reads.. rx_address(31:0) | rx_data(31:0)
257  tx_data(63 downto 32) <= rx_addr(31 downto 0);
258  process(MASTER_CLK)
259  begin
260  if (rising_edge(MASTER_CLK) and rx_wren='1') then
261  tx_data(15 downto 0) <= rx_data(15 downto 0);
262  end if;
263  end process;
264 
265  process(CLK15NS)
266  begin
267  if (rising_edge(CLK15NS)) then
268  tx_data(31 downto 24) <= std_logic_vector(unsigned(tx_data(31 downto 24)) + 1);
269  end if;
270  end process;
271 
272  process(secondary_clk)
273  begin
274  if (rising_edge(secondary_clk)) then
275  tx_data(23 downto 16) <= std_logic_vector(unsigned(tx_data(23 downto 16)) + 1);
276  end if;
277  end process;
278 
279  -----------------------
280  ----------------------- IBUF 's
281 
282  IBUF_PHY_RXDV : IBUF port map (I =>PHY_RXCTL_RXDV, O =>GMII_RX_DV_0_sig);
283 
284 --removed by script (others => '0'); -- for RGMII or SGMII
285 
286  IBUF_PHY_RXD7 : IBUF port map (I =>PHY_RXD7, O =>GMII_RXD_0_sig(7));
287  IBUF_PHY_RXD6 : IBUF port map (I =>PHY_RXD6, O =>GMII_RXD_0_sig(6));
288  IBUF_PHY_RXD5 : IBUF port map (I =>PHY_RXD5, O =>GMII_RXD_0_sig(5));
289  IBUF_PHY_RXD4 : IBUF port map (I =>PHY_RXD4, O =>GMII_RXD_0_sig(4));
290  IBUF_PHY_RXD3 : IBUF port map (I =>PHY_RXD3, O =>GMII_RXD_0_sig(3));
291  IBUF_PHY_RXD2 : IBUF port map (I =>PHY_RXD2, O =>GMII_RXD_0_sig(2));
292  IBUF_PHY_RXD1 : IBUF port map (I =>PHY_RXD1, O =>GMII_RXD_0_sig(1));
293  IBUF_PHY_RXD0 : IBUF port map (I =>PHY_RXD0, O =>GMII_RXD_0_sig(0));
294 
295  GMII_RX_ER_0_sig <= '0';
296 
297  IBUF_PHY_RXCLK : IBUFG port map (I =>PHY_RXCLK, O =>MASTER_CLK);
298 
299  -----------------------
300  ----------------------- OBUF 's
301 
302  --OBUF_PHY_RESET : OBUF port map (I=>'1', O=>PHY_RESET); --hold not reset
303 
304  OBUF_PHY_TXER : OBUF port map (I =>PHY_TXER_sig, O =>PHY_TXER);
305 
306  OBUF_PHY_TXEN : OBUF port map (I =>PHY_TXEN_sig, O =>PHY_TXCTL_TXEN);
307 
308  OBUF_PHY_TXCLK : OBUF port map (I =>GTX_CLK_0_sig, O =>PHY_TXC_GTXCLK);
309 
310  OBUF_PHY_TXD7 : OBUF port map (I =>PHY_TXD_sig(7), O =>PHY_TXD7);
311  OBUF_PHY_TXD6 : OBUF port map (I =>PHY_TXD_sig(6), O =>PHY_TXD6);
312  OBUF_PHY_TXD5 : OBUF port map (I =>PHY_TXD_sig(5), O =>PHY_TXD5);
313  OBUF_PHY_TXD4 : OBUF port map (I =>PHY_TXD_sig(4), O =>PHY_TXD4);
314  OBUF_PHY_TXD3 : OBUF port map (I =>PHY_TXD_sig(3), O =>PHY_TXD3);
315  OBUF_PHY_TXD2 : OBUF port map (I =>PHY_TXD_sig(2), O =>PHY_TXD2);
316  OBUF_PHY_TXD1 : OBUF port map (I =>PHY_TXD_sig(1), O =>PHY_TXD1);
317  OBUF_PHY_TXD0 : OBUF port map (I =>PHY_TXD_sig(0), O =>PHY_TXD0);
318 
319 
320 end BEHAVIORAL;
321