otsdaq_prepmodernization  v2_04_02
GEC_TX_CTL_8.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : GEC_TX_CTL_8
4 -- Design : CAPTAN
5 -- Author : aprosser
6 -- Company : CD_CEPA_ESE
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : u:\CAPTAN\Data_Conversion_Board\CAPTAN\CAPTAN\compile\GEC_TX_CTL_8.vhd
11 -- Generated : 07/31/08 17:14:54
12 -- From : u:/CAPTAN/Data_Conversion_Board/CAPTAN/CAPTAN/src/GEC_TX_CTL_8.asf
13 -- By : FSM2VHDL ver. 5.0.0.9
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_arith.all;
24 use IEEE.std_logic_unsigned.all;
25 use params_package.all;
26 
27 entity gec_tx_ctl_8 is
28  port (
29  block_en: in STD_LOGIC;
30  clk: in STD_LOGIC;
31  data_fifo_empty: in STD_LOGIC;
32  data_fifo_rd_data: in STD_LOGIC_VECTOR (63 downto 0);
33  data_fifo_rderr: in STD_LOGIC;
34  delay_count: in STD_LOGIC;
35  gec_user_busy: in STD_LOGIC;
36  gec_user_tx_enable_out: in STD_LOGIC;
37  info_fifo_empty: in STD_LOGIC;
38  info_fifo_rd_data: in STD_LOGIC_VECTOR (15 downto 0);
39  info_fifo_rderr: in STD_LOGIC;
40  reset_n: in STD_LOGIC;
41  clear_delay_count: out STD_LOGIC;
42  data_fifo_rden: out STD_LOGIC;
43  data_fifo_rden_en: out STD_LOGIC;
44  gec_user_trigger: out STD_LOGIC;
45  gec_user_tx_data_in: out STD_LOGIC_VECTOR (7 downto 0);
46  gec_user_tx_size_in: out STD_LOGIC_VECTOR (10 downto 0);
47  info_fifo_rden: out STD_LOGIC;
48  start_delay_count: out STD_LOGIC);
49 end gec_tx_ctl_8;
50 
51 architecture gec_tx_ctl_8 of GEC_TX_CTL_8 is
52 
53 -- diagram signals declarations
54 signal byte_count: STD_LOGIC_VECTOR (2 downto 0);
55 signal data_fifo_rd_data_reg: STD_LOGIC_VECTOR (63 downto 0);
56 signal q_w_count: STD_LOGIC_VECTOR (7 downto 0);
57 signal tx_data_count: STD_LOGIC_VECTOR (10 downto 0);
58 
59 -- SYMBOLIC ENCODED state machine: Sreg0
60 type Sreg0_type is (
61  idle, enabled, chk_busy, txmtdone, data_rdy_read_Ififo, trgrd, data_rdy_savecount, txmt_xmiting, S1, S2, txmt_S3, S4
62 );
63 -- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding
64 
65 signal Sreg0: Sreg0_type;
66 
67 begin
68 
69 
70 ----------------------------------------------------------------------
71 -- Machine: Sreg0
72 ----------------------------------------------------------------------
73 Sreg0_machine: process (clk)
74 begin
75  if clk'event and clk = '1' then
76  if reset_n = '0' then
77  Sreg0 <= idle;
78  -- Set default values for outputs, signals and variables
79  -- ...
80  gec_user_trigger <= '0';
81  gec_user_tx_size_in <= v_11_0;
82  q_w_count <= v_8_0;
83  tx_data_count <= v_11_0;
84  info_fifo_rden <= '0';
85  data_fifo_rden <= '0';
86  data_fifo_rden_en <= '0';
87  data_fifo_rd_data_reg <= v_64_0;
88  byte_count <= "000";
89  start_delay_count <= '0';
90  clear_delay_count <= '0';
91  else
92  -- Set default values for outputs, signals and variables
93  -- ...
94  case Sreg0 is
95  when idle =>
96  if block_en = '1' then
97  Sreg0 <= enabled;
98  elsif block_en = '0' then
99  Sreg0 <= idle;
100  end if;
101  when enabled =>
102  if block_en = '0' then
103  Sreg0 <= idle;
104  elsif (info_fifo_empty = '0' and block_en = '1') and
105  delay_count = '0' then -- FIFO has an entry and no more delay needed
106  Sreg0 <= data_rdy_read_Ififo;
107  clear_delay_count <= '1';
108  info_fifo_rden <= '1';
109  -- Read the info word
110  byte_count <= "000";
111  elsif (info_fifo_empty = '1' and block_en = '1') or
112  delay_count = '1' then -- FIFO is empty or delay not complete
113  Sreg0 <= enabled;
114  end if;
115  when chk_busy =>
116  if gec_user_busy = '0' then
117  Sreg0 <= trgrd;
118  gec_user_trigger <= '1';
119  -- GEC not busy
120  -- assert trigger to GEC
121  if (tx_data_count /= v_11_1) then
122  data_fifo_rd_data_reg <= data_fifo_rd_data;
123  -- prepare first quad word if there is one
124  end if;
125  elsif gec_user_busy = '1' then
126  Sreg0 <= chk_busy;
127  data_fifo_rden <= '0';
128  -- finished reading quad word fifo for first quad word
129  end if;
130  when txmtdone =>
131  if block_en = '0' then
132  Sreg0 <= idle;
133  elsif block_en = '1' then
134  Sreg0 <= enabled;
135  end if;
136  when trgrd =>
137  if gec_user_tx_enable_out = '1' then
138  Sreg0 <= txmt_xmiting;
139  if (tx_data_count = v_11_1) then
140  data_fifo_rden_en <= '0';
141  -- turn off FIFO accesses early
142  -- only one byte is requested and
143  -- it has been preloaded (this should
144  -- not happen in loopback tests
145  else
146  -- update the data presented to the GEC
147  gec_user_tx_data_in <= data_fifo_rd_data(63 downto 56);
148  -- increment the byte count
149  byte_count <= "001";
150  end if;
151  -- decrement count of bytes;
152  -- user_tx_enable_out from the GEC is
153  -- enabling read operations on the data
154  -- FIFO
155  elsif gec_user_tx_enable_out = '0' then -- wait for enable tx reply
156  Sreg0 <= trgrd;
157  end if;
158  when S1 =>
159  Sreg0 <= S2;
160  tx_data_count <= tx_data_count + v_11_1;
161  -- add return code byte to
162  -- produce the final number of bytes
163  start_delay_count <= '1';
164  when S2 =>
165  Sreg0 <= S4;
166  gec_user_tx_size_in <= tx_data_count;
167  -- present byte count to GEC
168  if (tx_data_count /= v_11_1) then
169  -- read a quad word for initialization
170  data_fifo_rden_en <= '1';
171  data_fifo_rden <= '1';
172  end if;
173  when S4 =>
174  Sreg0 <= chk_busy;
175  data_fifo_rden <= '0';
176  start_delay_count <= '0';
177  when data_rdy_read_Ififo =>
178  Sreg0 <= data_rdy_savecount;
179  info_fifo_rden <= '0';
180  -- terminate info word read
181  clear_delay_count <= '0';
182  when data_rdy_savecount =>
183  Sreg0 <= S1;
184  q_w_count <= info_fifo_rd_data(15 downto 8);
185  -- get number of quad words
186  gec_user_tx_data_in <= info_fifo_rd_data(7 downto 0);
187  -- assert the return code to the GEC
188  -- when Ryan's enable out signal goes high
189  -- the return code is there already
190  tx_data_count <= info_fifo_rd_data(15 downto 8) & "000";
191  -- compute number of bytes in quad words to be returned to PC
192  -- multiplies quad word count by 8
193  data_fifo_rden <= '0';
194  -- terminate first data word read
195  when txmt_xmiting =>
196  if tx_data_count = v_11_1 then
197  Sreg0 <= txmt_S3;
198  gec_user_trigger <= '0';
199  gec_user_tx_size_in <= v_11_0;
200  tx_data_count <= v_11_0;
201  info_fifo_rden <= '0';
202  data_fifo_rden <= '0';
203  data_fifo_rden_en <= '0';
204  elsif q_w_count /= v_8_0 then
205  Sreg0 <= txmt_xmiting;
206  case byte_count is
207  when "000" =>
208  byte_count <= byte_count + v_3_1;
209  gec_user_tx_data_in <= data_fifo_rd_data_reg(63 downto 56);
210  when "001" =>
211  byte_count <= byte_count + v_3_1;
212  gec_user_tx_data_in <= data_fifo_rd_data_reg(55 downto 48);
213  when "010" =>
214  byte_count <= byte_count + v_3_1;
215  gec_user_tx_data_in <= data_fifo_rd_data_reg(47 downto 40);
216  -- Read a new data quad word with plenty of time to spare
217  -- Jefferson did this to compensate for commenting
218  --out the action done when q_w_count =v_5_1
219  if (q_w_count > v_5_1)then
220  data_fifo_rden <= '1';
221  end if;
222  when "011" =>
223  byte_count <= byte_count + v_3_1;
224  gec_user_tx_data_in <= data_fifo_rd_data_reg(39 downto 32);
225  -- Finish read a new data quad word with plenty of time to spare
226  data_fifo_rden <= '0';
227  when "100" =>
228  byte_count <= byte_count + v_3_1;
229  gec_user_tx_data_in <= data_fifo_rd_data_reg(31 downto 24);
230  -- at this point, the data_fifo_rd_data lines have the
231  -- next quad word sitting on them
232  when "101" =>
233  byte_count <= byte_count + v_3_1;
234  gec_user_tx_data_in <= data_fifo_rd_data_reg(23 downto 16);
235  when "110" =>
236  byte_count <= byte_count + v_3_1;
237  gec_user_tx_data_in <= data_fifo_rd_data_reg(15 downto 8);
238  when "111" =>
239  byte_count <= "000";
240  gec_user_tx_data_in <= data_fifo_rd_data_reg(7 downto 0);
241  -- read another quad word
242  data_fifo_rd_data_reg <= data_fifo_rd_data;
243  -- we latch the data into the internal register
244  -- data_fifo_rd_data_reg
245  q_w_count <= q_w_count - v_5_1;
246  -- decrement the quad word count after we process the 8 bytes
247  -- in a quad word
248  when others =>
249  byte_count <= "000";
250  --null;
251  end case;
252  elsif q_w_count = v_8_0 then
253  Sreg0 <= txmt_S3;
254  gec_user_trigger <= '0';
255  gec_user_tx_size_in <= v_11_0;
256  tx_data_count <= v_11_0;
257  info_fifo_rden <= '0';
258  data_fifo_rden <= '0';
259  data_fifo_rden_en <= '0';
260  --Jefferson commented this out because it caused only
261  -- the first case (when "000") was being run
262  -- I think it is because this is not a loop
263  --case byte_count is
264  -- when "000" =>
265  -- byte_count <= byte_count + v_3_1;
266  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(7 downto 0);
267  -- when "001" =>
268  -- byte_count <= byte_count + v_3_1;
269  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(15 downto 8);
270  -- when "010" =>
271  -- byte_count <= byte_count + v_3_1;
272  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(23 downto 16);
273  ---- Read a new data quad word with plenty of time to spare
274  ---- data_fifo_rden <= '1';
275  -- when "011" =>
276  -- byte_count <= byte_count + v_3_1;
277  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(31 downto 24);
278  ---- Finish read a new data quad word with plenty of time to spare
279  -- data_fifo_rden <= '0';
280  -- when "100" =>
281  -- byte_count <= byte_count + v_3_1;
282  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(39 downto 32);
283  ---- at this point, the data_fifo_rd_data lines have the
284  ---- next quad word sitting on them
285  -- when "101" =>
286  -- byte_count <= byte_count + v_3_1;
287  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(47 downto 40);
288  -- when "110" =>
289  -- byte_count <= byte_count + v_3_1;
290  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(55 downto 48);
291  -- when "111" =>
292  -- byte_count <= "000";
293  -- gec_user_tx_data_in <= data_fifo_rd_data_reg(63 downto 56);
294  ---- read another quad word
295  ---- data_fifo_rd_data_reg <= data_fifo_rd_data;
296  ---- we latch the data into the internal register
297  ---- data_fifo_rd_data_reg
298  ---- q_w_count <= q_w_count - v_5_1;
299  ---- decrement the quad word count after we process the 8 bytes
300  ---- in a quad word
301  -- when others =>
302  -- byte_count <= "000";
303  -- --null;
304  --end case;
305  --
306  end if;
307  when txmt_S3 =>
308  Sreg0 <= txmtdone;
309  gec_user_trigger <= '0';
310  gec_user_tx_size_in <= v_11_0;
311  tx_data_count <= v_11_0;
312  info_fifo_rden <= '0';
313  data_fifo_rden <= '0';
314  data_fifo_rden_en <= '0';
315  gec_user_trigger <= '0';
316  gec_user_tx_size_in <= v_11_0;
317  tx_data_count <= v_11_0;
318  info_fifo_rden <= '0';
319  data_fifo_rden <= '0';
320  data_fifo_rden_en <= '0';
321  when others =>
322  null;
323  end case;
324  end if;
325  end if;
326 end process;
327 
328 end GEC_TX_CTL_8;