otsdaq_prepmodernization  v2_04_02
bmg_stim_gen.vhd
1 
2 
3 
4 --------------------------------------------------------------------------------
5 --
6 -- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
7 --
8 --------------------------------------------------------------------------------
9 --
10 -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
11 --
12 -- This file contains confidential and proprietary information
13 -- of Xilinx, Inc. and is protected under U.S. and
14 -- international copyright and other intellectual property
15 -- laws.
16 --
17 -- DISCLAIMER
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20 -- otherwise provided in a valid license issued to you by
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52 --
53 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
54 -- PART OF THIS FILE AT ALL TIMES.
55 
56 --------------------------------------------------------------------------------
57 --
58 -- Filename: bmg_stim_gen.vhd
59 --
60 -- Description:
61 -- Stimulus Generation For SRAM
62 -- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
63 -- simulation ends
64 --
65 --------------------------------------------------------------------------------
66 -- Author: IP Solutions Division
67 --
68 -- History: Sep 12, 2011 - First Release
69 --------------------------------------------------------------------------------
70 --
71 --------------------------------------------------------------------------------
72 -- Library Declarations
73 --------------------------------------------------------------------------------
74 LIBRARY IEEE;
75 USE IEEE.STD_LOGIC_1164.ALL;
76 USE IEEE.STD_LOGIC_ARITH.ALL;
77 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
78 USE IEEE.STD_LOGIC_MISC.ALL;
79 
80 LIBRARY work;
81 USE work.ALL;
82 
83 USE work.BMG_TB_PKG.ALL;
84 
85 
86 ENTITY REGISTER_LOGIC_SRAM IS
87  PORT(
88  Q : OUT STD_LOGIC;
89  CLK : IN STD_LOGIC;
90  RST : IN STD_LOGIC;
91  D : IN STD_LOGIC
92  );
93 END REGISTER_LOGIC_SRAM;
94 
95 ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
96  SIGNAL Q_O : STD_LOGIC :='0';
97 BEGIN
98  Q <= Q_O;
99  FF_BEH: PROCESS(CLK)
100  BEGIN
101  IF(RISING_EDGE(CLK)) THEN
102  IF(RST ='1') THEN
103  Q_O <= '0';
104  ELSE
105  Q_O <= D;
106  END IF;
107  END IF;
108  END PROCESS;
109 END REGISTER_ARCH;
110 
111 LIBRARY IEEE;
112 USE IEEE.STD_LOGIC_1164.ALL;
113 USE IEEE.STD_LOGIC_ARITH.ALL;
114 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
115 USE IEEE.STD_LOGIC_MISC.ALL;
116 
117 LIBRARY work;
118 USE work.ALL;
119 USE work.BMG_TB_PKG.ALL;
120 
121 
122 ENTITY BMG_STIM_GEN IS
123  PORT (
124  CLK : IN STD_LOGIC;
125  RST : IN STD_LOGIC;
126  ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
127  DINA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
128  WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
129  CHECK_DATA: OUT STD_LOGIC:='0'
130  );
131 END BMG_STIM_GEN;
132 
133 
134 ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
135 
136  CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
137  CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(64,64);
138  SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
139  SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
140  SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
141  SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
142  SIGNAL DINA_INT : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
143  SIGNAL DO_WRITE : STD_LOGIC := '0';
144  SIGNAL DO_READ : STD_LOGIC := '0';
145  SIGNAL COUNT_NO : INTEGER :=0;
146  SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
147 BEGIN
148  WRITE_ADDR_INT(9 DOWNTO 0) <= WRITE_ADDR(9 DOWNTO 0);
149  READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
150  ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
151  DINA <= DINA_INT ;
152 
153  CHECK_DATA <= DO_READ;
154 
155 RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
156  GENERIC MAP(
157  C_MAX_DEPTH => 1024
158  )
159  PORT MAP(
160  CLK => CLK,
161  RST => RST,
162  EN => DO_READ ,
163  LOAD => '0',
164  LOAD_VALUE => ZERO,
165  ADDR_OUT => READ_ADDR
166  );
167 
168 WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
169  GENERIC MAP(
170  C_MAX_DEPTH => 1024 )
171  PORT MAP(
172  CLK => CLK,
173  RST => RST,
174  EN => DO_WRITE,
175  LOAD => '0',
176  LOAD_VALUE => ZERO,
177  ADDR_OUT => WRITE_ADDR
178  );
179 
180 WR_DATA_GEN_INST:ENTITY work.DATA_GEN
181  GENERIC MAP (
182  DATA_GEN_WIDTH => 64,
183  DOUT_WIDTH => 64,
184  DATA_PART_CNT => DATA_PART_CNT_A,
185  SEED => 2
186  )
187  PORT MAP (
188  CLK => CLK,
189  RST => RST,
190  EN => DO_WRITE ,
191  DATA_OUT => DINA_INT
192  );
193 
194 WR_RD_PROCESS: PROCESS (CLK)
195 BEGIN
196  IF(RISING_EDGE(CLK)) THEN
197  IF(RST='1') THEN
198  DO_WRITE <= '0';
199  DO_READ <= '0';
200  COUNT_NO <= 0 ;
201  ELSIF(COUNT_NO < 4) THEN
202  DO_WRITE <= '1';
203  DO_READ <= '0';
204  COUNT_NO <= COUNT_NO + 1;
205  ELSIF(COUNT_NO< 8) THEN
206  DO_WRITE <= '0';
207  DO_READ <= '1';
208  COUNT_NO <= COUNT_NO + 1;
209  ELSIF(COUNT_NO=8) THEN
210  DO_WRITE <= '0';
211  DO_READ <= '0';
212  COUNT_NO <= 0 ;
213  END IF;
214  END IF;
215 END PROCESS;
216 
217 BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
218 BEGIN
219  DFF_RIGHT: IF I=0 GENERATE
220  BEGIN
221  SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
222  PORT MAP(
223  Q => DO_READ_REG(0),
224  CLK => CLK,
225  RST => RST,
226  D => DO_READ
227  );
228  END GENERATE DFF_RIGHT;
229  DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
230  BEGIN
231  SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
232  PORT MAP(
233  Q => DO_READ_REG (I),
234  CLK => CLK,
235  RST => RST,
236  D => DO_READ_REG (I-1)
237  );
238  END GENERATE DFF_OTHERS;
239 END GENERATE BEGIN_SHIFT_REG;
240 
241  WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
242 
243 END ARCHITECTURE;