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FIFO_SIM_tb.vhd
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--------------------------------------------------------------------------------
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-- Company: Fermilab
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-- Engineer: Collin Bradford
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--
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-- Create Date: 14:51:35 07/06/2016
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-- Design Name:
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-- Module Name: D:/cbradford/WorkingExampleCollinDebug/GPS_ADC_/GEL_CAPTAN/FIFO_SIM_tb.vhd
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-- Project Name: dig_mac
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: FIFO_SIM
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY
ieee
;
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USE
ieee.std_logic_1164.
ALL
;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY
FIFO_SIM_tb
IS
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END
FIFO_SIM_tb
;
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ARCHITECTURE
behavior
OF
FIFO_SIM_tb
IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT
FIFO_SIM
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PORT
(
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rst :
IN
std_logic
;
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clk :
IN
std_logic
;
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full :
IN
std_logic
;
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data_out :
OUT
std_logic_vector
(
31
downto
0
);
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wr_en :
OUT
std_logic
;
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FIFO_RESET :
OUT
std_logic
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);
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END
COMPONENT
;
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--Inputs
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signal
rst
:
std_logic
:=
'
1
'
;
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signal
clk
:
std_logic
:=
'
0
'
;
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signal
full
:
std_logic
:=
'
0
'
;
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--Outputs
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signal
data_out
:
std_logic_vector
(
31
downto
0
)
;
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signal
wr_en
:
std_logic
;
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signal
FIFO_RESET
:
std_logic
;
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-- Clock period definitions
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constant
clk_period
:
time
:=
10
ns
;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut:
FIFO_SIM
PORT
MAP
(
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rst => rst,
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clk => clk,
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full => full,
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data_out => data_out,
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wr_en => wr_en,
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FIFO_RESET => FIFO_RESET
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)
;
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-- Clock process definitions
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clk_process :
process
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begin
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clk
<=
'
0
'
;
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wait
for
clk_period
/
2
;
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clk
<=
'
1
'
;
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wait
for
clk_period
/
2
;
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end
process
;
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-- Stimulus process
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stim_proc:
process
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begin
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-- hold reset state for 100 ns.
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wait
for
100
ns
;
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rst
<=
'
0
'
;
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wait
for
clk_period
*
50
;
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full
<=
'
1
'
;
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wait
for
clk_period
*
10
;
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full
<=
'
0
'
;
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-- insert stimulus here
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wait
;
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end
process
;
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END
;
FIFO_SIM_tb
Definition:
FIFO_SIM_tb.vhd:35
FIFO_SIM
Definition:
FIFO_SIM.vhd:25
src
firmware
g-2
KickerControllerFirmware
GEL_CAPTAN
FIFO_SIM_tb.vhd
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