3 use IEEE.STD_LOGIC_1164.
ALL;
4 use IEEE.STD_LOGIC_ARITH.
ALL;
5 use IEEE.STD_LOGIC_UNSIGNED.
ALL;
7 use params_package.ALL;
13 MASTER_CLK : in ;
-- 125 MHz Ethernet Clock
16 BURST_END_PACKET: out ;
20 end burst_traffic_controller;
25 signal clocks_since_send : (33 downto 0);
26 signal writes_in_curr_burst : (7 downto 0);
33 if rising_edge(MASTER_CLK) then
35 -- keep pulses to only one clock
36 BURST_END_PACKET <= '0';
40 clocks_since_send <= (others => '0');
41 writes_in_curr_burst <= (others => '0');
45 if clocks_since_send /= '1' & x"00000000" then -- increment clocks since last burst packet send
46 clocks_since_send <= clocks_since_send + 1;
49 if BURST_WE = '1' then
51 if writes_in_curr_burst >= 181 then
52 writes_in_curr_burst <= (others => '0');
53 clocks_since_send <= (others => '0');
55 writes_in_curr_burst <= writes_in_curr_burst + 1;
60 -- check if between hits should end Burst Packet due to time out period
61 if writes_in_curr_burst /= 0 and
62 clocks_since_send >= '0' & x"0080" & '1' & x"E848" then--BURST_PERIOD_MAX & '1' & x"E848" then -- in ms : [<val> * 0x1E848] 125Mhz clocks is max wait
63 BURST_END_PACKET <= '1';
-- force end burst packet
64 clocks_since_send <= (others => '0');
65 writes_in_curr_burst <= (others => '0');