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FADC_WRITE_CTRL.vhd
1
----------------------------------------------------------------------------------
2
-- Company:
3
-- Engineer: Ryan Rivera, rrivera@fnal.gov
4
--
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-- Create Date: 11:09:15 07/28/2011
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-- Design Name:
7
-- Module Name: FADC_WRITE_CTRL - Behavioral
8
-- Project Name:
9
-- Target Devices:
10
-- Tool versions:
11
-- Description:
12
--
13
-- Dependencies:
14
--
15
-- Revision:
16
-- Revision 0.01 - File Created
17
-- Additional Comments:
18
--
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----------------------------------------------------------------------------------
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library
IEEE
;
21
use
IEEE.std_logic_1164.
all
;
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use
IEEE.std_logic_arith.
all
;
23
use
IEEE.std_logic_unsigned.
all
;
24
use
fadc_params_package.all
;
25
26
-- Uncomment the following library declaration if using
27
-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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30
-- Uncomment the following library declaration if instantiating
31
-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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35
entity
FADC_WRITE_CTRL
is
36
Port
(
fadc_dclk
:
in
STD_LOGIC
;
37
reset
:
in
STD_LOGIC
;
38
trigger
:
in
STD_LOGIC
;
39
rdy_for_trig
:
in
STD_LOGIC
;
--from readout controller
40
post_trig_count
:
in
STD_LOGIC_VECTOR
(
MEM_ADDR_SIZE
-
1
downto
0
)
;
-- num of samples to take after trigger
41
we_rise
:
out
STD_LOGIC
;
42
waddr_rise
:
out
STD_LOGIC_VECTOR
(
MEM_ADDR_SIZE
-
1
downto
0
)
;
43
dout_dbg_rise
:
out
STD_LOGIC_VECTOR
(
31
downto
0
)
;
44
dout_dbg_fall
:
out
STD_LOGIC_VECTOR
(
31
downto
0
)
;
45
we_fall
:
out
STD_LOGIC
;
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waddr_fall
:
out
STD_LOGIC_VECTOR
(
MEM_ADDR_SIZE
-
1
downto
0
)
;
47
done
:
out
STD_LOGIC
)
;
-- rising edge of done indicates ready to read
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end
FADC_WRITE_CTRL
;
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50
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architecture
Behavioral
of
FADC_WRITE_CTRL
is
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signal
cnt
:
integer
range
0
to
2
*
*
MEM_ADDR_SIZE
-
1
;
--count number of samples after trigger
54
signal
trigger_old
:
STD_LOGIC
;
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signal
rdy_for_trig_old
:
STD_LOGIC
;
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signal
actually_ready
:
STD_LOGIC
;
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signal
done_sig
:
STD_LOGIC
;
58
signal
we_rise_sig
:
STD_LOGIC
;
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signal
halt
:
STD_LOGIC
;
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signal
waddr_rise_sig
:
STD_LOGIC_VECTOR
(
MEM_ADDR_SIZE
-
1
downto
0
)
;
61
signal
waddr_fall_sig
:
STD_LOGIC_VECTOR
(
MEM_ADDR_SIZE
-
1
downto
0
)
;
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63
begin
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65
--desc:
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--on rising edge
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--we_rise=0.
68
--if reset, waddr_rise=0, done=1.
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--if rdy_for_trig and done and trigger rising edge, cnt = 0, done=0.
70
--if rising rdy_for_trig, halt=0.
71
--if cnt = post_trig_count and done=0, done=1, halt = 1; else if halt=0 we_rise = 1,waddr_rise++. --reason why 0 is invalid
72
--if done=0, cnt++.
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--on falling edge
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--during reset, we_fall=0, waddr_fall=0.
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--if we_rise = 1, we_fall = 1, waddr_fall++; else we_fall = 0.
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done
<=
halt
;
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we_rise
<=
we_rise_sig
;
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waddr_rise
<=
waddr_rise_sig
;
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waddr_fall
<=
waddr_fall_sig
;
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dout_dbg_rise
<=
x
"1"
&
"00"
&
waddr_rise_sig
&
x
"0"
&
"00"
&
waddr_rise_sig
;
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dout_dbg_fall
<=
x
"3"
&
"00"
&
waddr_fall_sig
&
x
"2"
&
"00"
&
waddr_fall_sig
;
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process
(fadc_dclk)
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begin
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------------------------------------
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--================================-- RISING EDGE PROCESS
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------------------------------------
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if
rising_edge
(
fadc_dclk
)
then
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we_rise_sig
<=
'
0
'
;
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trigger_old
<=
trigger
;
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rdy_for_trig_old
<=
rdy_for_trig
;
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if
reset
=
'
1
'
then
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waddr_rise_sig
<=
(
others
=
>
'
0
'
)
;
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done_sig
<=
'
1
'
;
--done is 0 while counting after trigger
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halt
<=
'
0
'
;
--halt is 1 once counting has stopped
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actually_ready
<=
'
0
'
;
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cnt
<=
0
;
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else
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if
actually_ready
=
'
1
'
and
trigger_old
=
'
0
'
and
trigger
=
'
1
'
then
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cnt
<=
0
;
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actually_ready
<=
'
0
'
;
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done_sig
<=
'
0
'
;
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end
if
;
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if
rdy_for_trig_old
=
'
0
'
and
rdy_for_trig
=
'
1
'
and
halt
=
'
1
'
then
--come out of done
112
halt
<=
'
0
'
;
--continuously take data
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end
if
;
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if
actually_ready
=
'
0
'
and
halt
=
'
0
'
and
done_sig
=
'
1
'
then
--wait while buffer fills up before taking data again
116
117
if
cnt
=
2
*
*
MEM_ADDR_SIZE
-
1
then
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actually_ready
<=
'
1
'
;
--continuously take data
119
else
120
cnt
<=
cnt
+
1
;
121
end
if
;
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end
if
;
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-- above is coming out of last read and receiving next trigger
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---------------
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-- below is the read process
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if
conv_std_logic_vector
(
cnt
,
10
)
=
post_trig_count
and
done_sig
=
'
0
'
then
130
done_sig
<=
'
1
'
;
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halt
<=
'
1
'
;
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cnt
<=
0
;
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else
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if
halt
=
'
0
'
then
135
we_rise_sig
<=
'
1
'
;
136
waddr_rise_sig
<=
waddr_rise_sig
+
1
;
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end
if
;
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139
if
done_sig
=
'
0
'
then
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if
cnt
=
2
*
*
MEM_ADDR_SIZE
-
1
then
141
cnt
<=
0
;
142
else
143
cnt
<=
cnt
+
1
;
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end
if
;
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end
if
;
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end
if
;
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end
if
;
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end
if
;
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------------------------------------
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--================================-- FALLING EDGE PROCESS
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------------------------------------
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if
falling_edge
(
fadc_dclk
)
then
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159
we_fall
<=
'
0
'
;
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if
reset
=
'
1
'
then
162
waddr_fall_sig
<=
(
others
=
>
'
0
'
)
;
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elsif
we_rise_sig
=
'
1
'
then
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we_fall
<=
'
1
'
;
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waddr_fall_sig
<=
waddr_fall_sig
+
1
;
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end
if
;
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end
if
;
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end
process
;
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end
Behavioral
;
FADC_WRITE_CTRL
Definition:
FADC_WRITE_CTRL.vhd:35
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FADC_WRITE_CTRL.vhd
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