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FADC_READ_CTRL.vhd
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:22:00 07/28/2011
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-- Design Name:
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-- Module Name: FADC_READ_CTRL - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library
IEEE
;
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use
IEEE.std_logic_1164.
all
;
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use
IEEE.std_logic_arith.
all
;
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use
IEEE.std_logic_unsigned.
all
;
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use
fadc_params_package.all
;
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entity
FADC_READ_CTRL
is
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Port
(
mclk
:
in
STD_LOGIC
;
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reset
:
in
STD_LOGIC
;
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done
:
in
STD_LOGIC
;
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rdata
:
in
STD_LOGIC_VECTOR
(
63
downto
0
)
;
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waddr_rise
:
in
STD_LOGIC_VECTOR
(
MEM_ADDR_SIZE
-
1
downto
0
)
;
--use as starting point
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raddr
:
out
STD_LOGIC_VECTOR
(
MEM_ADDR_SIZE
-
1
downto
0
)
;
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burst_we
:
out
STD_LOGIC
;
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burst_end_packet
:
out
STD_LOGIC
;
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burst_data
:
out
STD_LOGIC_VECTOR
(
63
downto
0
)
;
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rdy_for_trig
:
out
STD_LOGIC
)
;
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end
FADC_READ_CTRL
;
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architecture
Behavioral
of
FADC_READ_CTRL
is
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signal
reading
:
STD_LOGIC
;
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signal
rdy_for_trig_sig
:
STD_LOGIC
;
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signal
delay_state
:
STD_LOGIC
;
--need to delay because writing 64 bits every MCLK overloads Ethernet
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signal
cnt
:
integer
range
0
to
15
;
-- delay for ethernet to catch up
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signal
raddr_sig
:
STD_LOGIC_VECTOR
(
MEM_ADDR_SIZE
-
1
downto
0
)
;
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signal
done_old
:
STD_LOGIC
;
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begin
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--desc:
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--rdy_for_trig = not (reset or reading).
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--if reset, burst_we=0, burst_data=0xffffffffffffffff, reading=0.
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--if rising edge of done, cnt=0, reading=1, burst_we=1, raddr= waddr_rise. --write all F's
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--if reading = 1, cnt++, raddr--, burst_data = rdata. --first time data is from address = waddr_rise
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--if raddr_sig = waddr_rise and reading_old = '1', reading = 0, burst_we=0.
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--ADD BURST END PACKET!!!
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raddr
<=
raddr_sig
;
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rdy_for_trig
<=
rdy_for_trig_sig
;
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process
(mclk)
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begin
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if
rising_edge
(
mclk
)
then
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burst_we
<=
'
0
'
;
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burst_end_packet
<=
'
0
'
;
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done_old
<=
done
;
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if
reset
=
'
1
'
then
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reading
<=
'
0
'
;
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delay_state
<=
'
0
'
;
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cnt
<=
0
;
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burst_data
<=
(
others
=
>
'
1
'
)
;
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rdy_for_trig_sig
<=
'
0
'
;
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else
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if
reading
=
'
1
'
and
delay_state
=
'
1
'
then
-- DELAY STATE
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cnt
<=
cnt
+
1
;
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if
cnt
=
3
then
--give RAM a few clocks to stabilize read data
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burst_data
<=
rdata
;
--first time data is from address = waddr_rise
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--burst_data <= rdata(63 downto 24) & "0000" & waddr_rise & raddr_sig; --FOR DEBUGGING
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burst_we
<=
'
1
'
;
--write fadc data
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elsif
cnt
=
4
then
--give 1 extra clock before changing raddr
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raddr_sig
<=
raddr_sig
-
1
;
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elsif
cnt
=
BURST_WE_DELAY
then
--delay next write for some clocks
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cnt
<=
0
;
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delay_state
<=
'
0
'
;
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if
raddr_sig
=
waddr_rise
then
-- gone all the way around.. (delay state is just used to avoid initial case)
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reading
<=
'
0
'
;
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burst_end_packet
<=
'
1
'
;
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burst_data
<=
(
others
=
>
'
1
'
)
;
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end
if
;
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end
if
;
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elsif
reading
=
'
1
'
then
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delay_state
<=
'
1
'
;
--got to delay state
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elsif
rdy_for_trig_sig
=
'
1
'
and
reading
=
'
0
'
and
done_old
=
'
0
'
and
done
=
'
1
'
then
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reading
<=
'
1
'
;
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burst_we
<=
'
1
'
;
--write all F's
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raddr_sig
<=
waddr_rise
;
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burst_data
<=
(
others
=
>
'
1
'
)
;
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rdy_for_trig_sig
<=
'
0
'
;
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delay_state
<=
'
0
'
;
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cnt
<=
0
;
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else
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rdy_for_trig_sig
<=
'
1
'
;
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end
if
;
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end
if
;
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end
if
;
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end
process
;
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end
Behavioral
;
FADC_READ_CTRL
Definition:
FADC_READ_CTRL.vhd:27
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FADC_READ_CTRL.vhd
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