otsdaq_prepmodernization  v2_04_02
FIFO_SIM_tb.vhd
1 --------------------------------------------------------------------------------
2 -- Company: Fermilab
3 -- Engineer: Collin Bradford
4 --
5 -- Create Date: 14:51:35 07/06/2016
6 -- Design Name:
7 -- Module Name: D:/cbradford/WorkingExampleCollinDebug/GPS_ADC_/GEL_CAPTAN/FIFO_SIM_tb.vhd
8 -- Project Name: dig_mac
9 -- Target Device:
10 -- Tool versions:
11 -- Description:
12 --
13 -- VHDL Test Bench Created by ISE for module: FIFO_SIM
14 --
15 -- Dependencies:
16 --
17 -- Revision:
18 -- Revision 0.01 - File Created
19 -- Additional Comments:
20 --
21 -- Notes:
22 -- This testbench has been automatically generated using types std_logic and
23 -- std_logic_vector for the ports of the unit under test. Xilinx recommends
24 -- that these types always be used for the top-level I/O of a design in order
25 -- to guarantee that the testbench will bind correctly to the post-implementation
26 -- simulation model.
27 --------------------------------------------------------------------------------
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
30 
31 -- Uncomment the following library declaration if using
32 -- arithmetic functions with Signed or Unsigned values
33 --USE ieee.numeric_std.ALL;
34 
35 ENTITY FIFO_SIM_tb IS
36 END FIFO_SIM_tb;
37 
38 ARCHITECTURE behavior OF FIFO_SIM_tb IS
39 
40  -- Component Declaration for the Unit Under Test (UUT)
41 
42  COMPONENT FIFO_SIM
43  PORT(
44  rst : IN std_logic;
45  clk : IN std_logic;
46  full : IN std_logic;
47  data_out : OUT std_logic_vector(31 downto 0);
48  wr_en : OUT std_logic;
49  FIFO_RESET : OUT std_logic
50  );
51  END COMPONENT;
52 
53 
54  --Inputs
55  signal rst : std_logic := '1';
56  signal clk : std_logic := '0';
57  signal full : std_logic := '0';
58 
59  --Outputs
60  signal data_out : std_logic_vector(31 downto 0);
61  signal wr_en : std_logic;
62  signal FIFO_RESET : std_logic;
63 
64  -- Clock period definitions
65  constant clk_period : time := 10 ns;
66 
67 BEGIN
68 
69  -- Instantiate the Unit Under Test (UUT)
70  uut: FIFO_SIM PORT MAP (
71  rst => rst,
72  clk => clk,
73  full => full,
74  data_out => data_out,
75  wr_en => wr_en,
76  FIFO_RESET => FIFO_RESET
77  );
78 
79  -- Clock process definitions
80  clk_process :process
81  begin
82  clk <= '0';
83  wait for clk_period/2;
84  clk <= '1';
85  wait for clk_period/2;
86  end process;
87 
88 
89  -- Stimulus process
90  stim_proc: process
91  begin
92  -- hold reset state for 100 ns.
93  wait for 100 ns;
94 
95  rst <= '0';
96 
97  wait for clk_period*50;
98 
99  full <= '1';
100 
101  wait for clk_period * 10;
102 
103  full <= '0';
104 
105  -- insert stimulus here
106 
107  wait;
108  end process;
109 
110 END;