|
otsdaq_prepmodernization
v2_04_01
|
Libraries | |
| ieee | |
| unisim | |
Use Clauses | |
| ieee.std_logic_1164.all | |
| ieee.std_logic_arith.all | |
| ieee.std_logic_unsigned.all | |
| unisim.vcomponents.all | |
Ports | |
| CLK | in std_logic |
| SRST | in std_logic |
| WR_EN | in std_logic |
| RD_EN | in std_logic |
| DIN | in std_logic_vector ( 48 - 1 downto 0 ) |
| DOUT | out std_logic_vector ( 48 - 1 downto 0 ) |
| FULL | out std_logic |
| EMPTY | out std_logic |
Definition at line 74 of file ADDR_FIFO_exdes.vhd.