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otsdaq_prepmodernization
v2_04_01
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Libraries | |
| IEEE | |
| UNISIM | |
Use Clauses | |
| IEEE.STD_LOGIC_1164.all | |
| IEEE.STD_LOGIC_ARITH.all | |
| IEEE.STD_LOGIC_UNSIGNED.all | |
| UNISIM.VCOMPONENTS.all | |
Ports | |
| WEA | in STD_LOGIC_VECTOR ( 0 downto 0 ) |
| ADDRA | in STD_LOGIC_VECTOR ( 9 downto 0 ) |
| DINA | in STD_LOGIC_VECTOR ( 63 downto 0 ) |
| DOUTA | out STD_LOGIC_VECTOR ( 63 downto 0 ) |
| CLKA | in STD_LOGIC |
Definition at line 88 of file EthernetRAM_exdes.vhd.