otsdaq_prepmodernization
v2_04_01
Return to top level
Main Page
Classes
Files
File List
RX_IN_LATCH.vhd
1
----------------------------------------------------------------------------------
2
-- Company:
3
-- Engineer:
4
--
5
-- Create Date: 16:11:47 03/18/2009
6
-- Design Name:
7
-- Module Name: RX_IN_LATCH - Behavioral
8
-- Project Name:
9
-- Target Devices:
10
-- Tool versions:
11
-- Description:
12
--
13
-- Dependencies:
14
--
15
-- Revision:
16
-- Revision 0.01 - File Created
17
-- Additional Comments:
18
--
19
----------------------------------------------------------------------------------
20
library
IEEE
;
21
use
IEEE.STD_LOGIC_1164.
ALL
;
22
use
IEEE.STD_LOGIC_ARITH.
ALL
;
23
use
IEEE.STD_LOGIC_UNSIGNED.
ALL
;
24
25
---- Uncomment the following library declaration if instantiating
26
---- any Xilinx primitives in this code.
27
--library UNISIM;
28
--use UNISIM.VComponents.all;
29
30
entity
RX_IN_LATCH
is
31
Port
(
clk
:
in
STD_LOGIC
;
32
dv
:
in
STD_LOGIC
;
33
er
:
in
STD_LOGIC
;
34
d
:
in
STD_LOGIC_VECTOR
(
7
downto
0
)
;
35
dvo
:
out
STD_LOGIC
;
36
ero
:
out
STD_LOGIC
;
37
do
:
out
STD_LOGIC_VECTOR
(
7
downto
0
)
)
;
38
end
RX_IN_LATCH
;
39
40
architecture
Behavioral
of
RX_IN_LATCH
is
41
42
begin
43
44
process
(clk)
45
begin
46
if
falling_edge
(
clk
)
then
47
dvo
<=
dv
;
48
ero
<=
er
;
49
do
<=
d
;
50
end
if
;
51
end
process
;
52
53
end
Behavioral
;
54
RX_IN_LATCH
Definition:
RX_IN_LATCH.vhd:30
src
firmware
g-2
KickerControllerFirmware
GEL_CAPTAN
RX_IN_LATCH.vhd
Generated on Fri Jun 28 2019 14:52:02 for otsdaq_prepmodernization by
1.8.5