otsdaq_prepmodernization  v2_04_01
ip_checksum_calc.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : Checksum Calc
4 -- Design : ethernet_controller
5 -- Author : Ryan Rivera
6 -- Company : FNAL
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : c:\HDL_Designs\dig_gec\ethernet_controller\compile\ip_checksum_calc.vhd
11 -- Generated : 03/20/09 15:19:30
12 -- From : c:/HDL_Designs/dig_gec/ethernet_controller/src/ip_checksum_calc.asf
13 -- By : FSM2VHDL ver. 5.0.5.6
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_arith.all;
24 use IEEE.std_logic_unsigned.all;
25 
26 entity ip_checksum_calc is
27  port (
28  addrs: in STD_LOGIC_VECTOR (7 downto 0);
29  clk: in STD_LOGIC;
30  length: in STD_LOGIC_VECTOR (10 downto 0);
31  reset: in STD_LOGIC;
32  trigger: in STD_LOGIC;
33  cs: out STD_LOGIC_VECTOR (15 downto 0));
34 end ip_checksum_calc;
35 
36 architecture ip_checksum_calc_arch of ip_checksum_calc is
37 
38 -- diagram signals declarations
39 signal addrs_sig: STD_LOGIC_VECTOR (16 downto 0);
40 signal cs_sig: STD_LOGIC_VECTOR (16 downto 0);
41 signal length_sig: STD_LOGIC_VECTOR (16 downto 0);
42 
43 -- SYMBOLIC ENCODED state machine: Sreg0
44 type Sreg0_type is (
45  S1, S2, S3, S4, S5, S6, S7
46 );
47 -- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding
48 
49 signal Sreg0: Sreg0_type;
50 
51 begin
52 
53 -- concurrent signals assignments
54 
55 -- Diagram ACTION
56 --inputs
57 addrs_sig(16 downto 8) <= '0' & x"85";
58 addrs_sig(7 downto 0) <= addrs;
59 length_sig(16 downto 11) <= (others => '0');
60 length_sig(10 downto 0) <= length;
61 --outputs
62 cs_proc: process(clk)
63 begin
64  if rising_edge(clk) then
65  if reset = '1' then
66  cs <= (others => '0');
67  elsif Sreg0 = S7 then
68  cs <= cs_sig(15 downto 0);
69  end if;
70  end if;
71 end process;
72 
73 ----------------------------------------------------------------------
74 -- Machine: Sreg0
75 ----------------------------------------------------------------------
76 Sreg0_machine: process (clk)
77 begin
78  if clk'event and clk = '1' then
79  if reset = '1' then
80  Sreg0 <= S1;
81  -- Set default values for outputs, signals and variables
82  -- ...
83  cs_sig <= '0' & x"00FA";
84  else
85  -- Set default values for outputs, signals and variables
86  -- ...
87  case Sreg0 is
88  when S1 =>
89  cs_sig <= '0' & x"00FA";
90  if trigger = '1' then
91  Sreg0 <= S2;
92  end if;
93  when S2 =>
94  cs_sig <= cs_sig + length_sig;
95  Sreg0 <= S3;
96  when S3 =>
97  if cs_sig(16) = '1' then
98  cs_sig(15 downto 0) <= cs_sig(15 downto 0) + 1;
99  cs_sig(16) <= '0';
100  end if;
101  Sreg0 <= S4;
102  when S4 =>
103  cs_sig <= cs_sig + addrs_sig;
104  Sreg0 <= S5;
105  when S5 =>
106  if cs_sig(16) = '1' then
107  cs_sig(15 downto 0) <= cs_sig(15 downto 0) + 1;
108  cs_sig(16) <= '0';
109  end if;
110  Sreg0 <= S6;
111  when S6 =>
112  cs_sig <= not cs_sig;
113  Sreg0 <= S7;
114  when S7 =>
115  Sreg0 <= S1;
116 --vhdl_cover_off
117  when others =>
118  null;
119 --vhdl_cover_on
120  end case;
121  end if;
122  end if;
123 end process;
124 
125 end ip_checksum_calc_arch;