otsdaq_prepmodernization  v2_04_01
TOP_LEVEL.vhd
1 --------------------------------------------------------------------------------
2 -- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
3 --------------------------------------------------------------------------------
4 -- ____ ____
5 -- / /\/ /
6 -- /___/ \ / Vendor: Xilinx
7 -- \ \ \/ Version : 9.2.03i
8 -- \ \ Application : sch2vhdl
9 -- / / Filename : TOP_LEVEL.vhf
10 -- /___/ /\ Timestamp : 01/25/2008 15:27:05
11 -- \ \ / \
12 -- \___\/\___\
13 --
14 --Command: C:\Xilinx_9_2\bin\nt\sch2vhdl.exe -intstyle ise -family virtex4 -flat -suppress -w C:/Xilinx_9_2/Projects/dig_mac_4GEL/TOP_LEVEL.sch TOP_LEVEL.vhf
15 --Design Name: TOP_LEVEL
16 --Device: virtex4
17 --Purpose:
18 -- This vhdl netlist is translated from an ECS schematic. It can be
19 -- synthesis and simulted, but it should not be modified.
20 --
21 
22 library ieee;
23 use ieee.std_logic_1164.ALL;
24 use ieee.numeric_std.ALL;
25 library UNISIM;
26 use UNISIM.Vcomponents.ALL;
27 
29  port ( I : in std_logic_vector (7 downto 0);
30  O : out std_logic_vector (7 downto 0));
31 end OBUF8_MXILINX_TOP_LEVEL;
32 
33 architecture BEHAVIORAL of OBUF8_MXILINX_TOP_LEVEL is
34  attribute IOSTANDARD : string ;
35  attribute CAPACITANCE : string ;
36  attribute SLEW : string ;
37  attribute DRIVE : string ;
38  attribute BOX_TYPE : string ;
39  component OBUF
40  port ( I : in std_logic;
41  O : out std_logic);
42  end component;
43  attribute IOSTANDARD of OBUF : component is "DEFAULT";
44  attribute CAPACITANCE of OBUF : component is "DONT_CARE";
45  attribute SLEW of OBUF : component is "SLOW";
46  attribute DRIVE of OBUF : component is "12";
47  attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
48 
49 begin
50  I_36_30 : OBUF
51  port map (I =>I(0),
52  O =>O(0));
53 
54  I_36_31 : OBUF
55  port map (I =>I(1),
56  O =>O(1));
57 
58  I_36_32 : OBUF
59  port map (I =>I(2),
60  O =>O(2));
61 
62  I_36_33 : OBUF
63  port map (I =>I(3),
64  O =>O (3));
65 
66  I_36_34 : OBUF
67  port map (I =>I(7),
68  O =>O(7));
69 
70  I_36_35 : OBUF
71  port map (I =>I(6),
72  O =>O(6));
73 
74  I_36_36 : OBUF
75  port map (I =>I(5),
76  O =>O(5));
77 
78  I_36_37 : OBUF
79  port map (I =>I(4),
80  O =>O(4));
81 
82 end BEHAVIORAL;
83 
84 
85 
86 library ieee;
87 use ieee.std_logic_1164.ALL;
88 use ieee.numeric_std.ALL;
89 library UNISIM;
90 use UNISIM.Vcomponents.ALL;
91 
93  port ( I : in std_logic_vector (7 downto 0);
94  O : out std_logic_vector (7 downto 0));
95 end IBUF8_MXILINX_TOP_LEVEL;
96 
97 architecture BEHAVIORAL of IBUF8_MXILINX_TOP_LEVEL is
98  attribute IOSTANDARD : string ;
99  attribute CAPACITANCE : string ;
100  attribute BOX_TYPE : string ;
101  component IBUF
102  port ( I : in std_logic;
103  O : out std_logic);
104  end component;
105  attribute IOSTANDARD of IBUF : component is "DEFAULT";
106  attribute CAPACITANCE of IBUF : component is "DONT_CARE";
107  attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
108 
109 begin
110  I_36_30 : IBUF
111  port map (I =>I(4),
112  O =>O(4));
113 
114  I_36_31 : IBUF
115  port map (I =>I(5),
116  O =>O(5));
117 
118  I_36_32 : IBUF
119  port map (I =>I(6),
120  O =>O(6));
121 
122  I_36_33 : IBUF
123  port map (I =>I(7),
124  O =>O(7));
125 
126  I_36_34 : IBUF
127  port map (I =>I(3),
128  O =>O(3));
129 
130  I_36_35 : IBUF
131  port map (I =>I(2),
132  O =>O(2));
133 
134  I_36_36 : IBUF
135  port map (I =>I(1),
136  O =>O(1));
137 
138  I_36_37 : IBUF
139  port map (I =>I(0),
140  O =>O(0));
141 
142 end BEHAVIORAL;
143 
144 
145 
146 library ieee;
147 use ieee.std_logic_1164.ALL;
148 use ieee.numeric_std.ALL;
149 library UNISIM;
150 use UNISIM.Vcomponents.ALL;
151 
152 entity TOP_LEVEL is
153  port ( GMII_RXD_0 : in std_logic_vector (7 downto 0);
154  GMII_RX_CLK_0 : in std_logic;
155  GMII_RX_DV_0 : in std_logic;
156  GMII_RX_ER_0 : in std_logic;
157  GTX_CLK_0 : out std_logic;
158  PHY_RESET : out std_logic;
159  PHY_TXD : out std_logic_vector (7 downto 0);
160  PHY_TXEN : out std_logic;
161  PHY_TXER : out std_logic);
162 end TOP_LEVEL;
163 
164 architecture BEHAVIORAL of TOP_LEVEL is
165  attribute IOSTANDARD : string ;
166  attribute CAPACITANCE : string ;
167  attribute SLEW : string ;
168  attribute DRIVE : string ;
169  attribute BOX_TYPE : string ;
170  attribute HU_SET : string ;
171  signal GMII_RXD_0_sig : std_logic_vector (7 downto 0);
172  signal GMII_RX_CLK_0_sig : std_logic;
173  signal GMII_RX_DV_0_sig : std_logic;
174  signal GMII_RX_ER_0_sig : std_logic;
175  signal GTX_CLK_0_sig : std_logic;
176  signal PHY_TXD_sig : std_logic_vector (7 downto 0);
177  signal PHY_TXEN_sig : std_logic;
178  signal PHY_TXER_sig : std_logic;
179  signal reset_n : std_logic;
180  signal user_test_mode : std_logic;
181  signal user_trigger : std_logic;
182  signal XLXN_316 : std_logic_vector (7 downto 0);
183  signal XLXN_317 : std_logic_vector (10 downto 0);
184  signal XLXN_318 : std_logic_vector (7 downto 0);
185  component OBUF
186  port ( I : in std_logic;
187  O : out std_logic);
188  end component;
189  attribute IOSTANDARD of OBUF : component is "DEFAULT";
190  attribute CAPACITANCE of OBUF : component is "DONT_CARE";
191  attribute SLEW of OBUF : component is "SLOW";
192  attribute DRIVE of OBUF : component is "12";
193  attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
194 
195  component fake_user_data
196  port ( addrs : out std_logic_vector (7 downto 0);
197  size : out std_logic_vector (10 downto 0);
198  data : out std_logic_vector (7 downto 0));
199  end component;
200 
201  component IBUF
202  port ( I : in std_logic;
203  O : out std_logic);
204  end component;
205  attribute IOSTANDARD of IBUF : component is "DEFAULT";
206  attribute CAPACITANCE of IBUF : component is "DONT_CARE";
207  attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
208 
209  component IBUF8_MXILINX_TOP_LEVEL
210  port ( I : in std_logic_vector (7 downto 0);
211  O : out std_logic_vector (7 downto 0));
212  end component;
213 
214  component OBUF8_MXILINX_TOP_LEVEL
215  port ( I : in std_logic_vector (7 downto 0);
216  O : out std_logic_vector (7 downto 0));
217  end component;
218 
219  component IBUFG
220  port ( I : in std_logic;
221  O : out std_logic);
222  end component;
223  attribute IOSTANDARD of IBUFG : component is "DEFAULT";
224  attribute CAPACITANCE of IBUFG : component is "DONT_CARE";
225  attribute BOX_TYPE of IBUFG : component is "BLACK_BOX";
226 
227  component gigabit_ethernet_controller
228  port ( user_tx_data_in : in std_logic_vector (7 downto 0);
229  user_tx_size_in : in std_logic_vector (10 downto 0);
230  user_addrs : in std_logic_vector (7 downto 0);
231  GMII_RXD : in std_logic_vector (7 downto 0);
232  GMII_RX_DV : in std_logic;
233  GMII_RX_ER : in std_logic;
234  GMII_RX_CLK : in std_logic;
235  user_test_mode : in std_logic;
236  user_trigger : in std_logic;
237  reset_n : in std_logic;
238  user_rx_size_out : out std_logic_vector (10 downto 0);
239  GMII_TX_EN : out std_logic;
240  GMII_TX_ER : out std_logic;
241  GTX_CLK : out std_logic;
242  user_busy : out std_logic;
243  user_rx_valid_out : out std_logic;
244  user_tx_enable_out : out std_logic;
245  user_rx_data_out : out std_logic_vector (7 downto 0);
246  GMII_TXD : out std_logic_vector (7 downto 0);
247  crc_err : out std_logic);
248  end component;
249 
250  component GND
251  port ( G : out std_logic);
252  end component;
253  attribute BOX_TYPE of GND : component is "BLACK_BOX";
254 
255  component VCC
256  port ( P : out std_logic);
257  end component;
258  attribute BOX_TYPE of VCC : component is "BLACK_BOX";
259 
260  attribute HU_SET of XLXI_180 : label is "XLXI_180_0";
261  attribute HU_SET of XLXI_195 : label is "XLXI_195_1";
262 begin
263  XLXI_17 : OBUF
264  port map (I =>reset_n,
265  O =>PHY_RESET );
266 
267  XLXI_143 : fake_user_data
268  port map (addrs(7 downto 0)=>XLXN_316(7 downto 0),
269  data(7 downto 0)=>XLXN_318(7 downto 0),
270  size(10 downto 0)=>XLXN_317(10 downto 0));
271 
272  XLXI_178 : IBUF
273  port map (I =>GMII_RX_DV_0,
274  O =>GMII_RX_DV_0_sig);
275 
276  XLXI_179 : IBUF
277  port map (I =>GMII_RX_ER_0,
278  O =>GMII_RX_ER_0_sig);
279 
280  XLXI_180 : IBUF8_MXILINX_TOP_LEVEL
281  port map (I(7 downto 0)=>GMII_RXD_0(7 downto 0),
282  O(7 downto 0)=>GMII_RXD_0_sig(7 downto 0));
283 
284  XLXI_192 : OBUF
285  port map (I =>GTX_CLK_0_sig,
286  O =>GTX_CLK_0 );
287 
288  XLXI_193 : OBUF
289  port map (I =>PHY_TXER_sig,
290  O =>PHY_TXER );
291 
292  XLXI_194 : OBUF
293  port map (I =>PHY_TXEN_sig,
294  O =>PHY_TXEN );
295 
296  XLXI_195 : OBUF8_MXILINX_TOP_LEVEL
297  port map (I(7 downto 0)=>PHY_TXD_sig(7 downto 0),
298  O(7 downto 0)=>PHY_TXD(7 downto 0));
299 
300  XLXI_237 : IBUFG
301  port map (I =>GMII_RX_CLK_0,
302  O =>GMII_RX_CLK_0_sig );
303 
304  XLXI_274 : gigabit_ethernet_controller
305  port map (GMII_RXD(7 downto 0)=>GMII_RXD_0_sig(7 downto 0),
306  GMII_RX_CLK =>GMII_RX_CLK_0_sig ,
307  GMII_RX_DV =>GMII_RX_DV_0_sig,
308  GMII_RX_ER =>GMII_RX_ER_0_sig,
309  reset_n=>reset_n ,
310  user_addrs(7 downto 0)=>XLXN_316(7 downto 0),
311  user_test_mode =>user_test_mode,
312  user_trigger =>user_trigger,
313  user_tx_data_in(7 downto 0)=>XLXN_318(7 downto 0),
314  user_tx_size_in(10 downto 0)=>XLXN_317(10 downto 0),
315  crc_err=>open,
316  GMII_TXD(7 downto 0)=>PHY_TXD_sig(7 downto 0),
317  GMII_TX_EN =>PHY_TXEN_sig,
318  GMII_TX_ER =>PHY_TXER_sig,
319  GTX_CLK=>GTX_CLK_0_sig ,
320  user_busy =>open,
321  user_rx_data_out =>open,
322  user_rx_size_out =>open,
323  user_rx_valid_out =>open,
324  user_tx_enable_out =>open);
325 
326  XLXI_275 : GND
327  port map (G =>user_test_mode);
328 
329  XLXI_276 : VCC
330  port map (P =>reset_n);
331 
332 end BEHAVIORAL;
333 
334