otsdaq_prepmodernization  v2_04_01
VERSION_BLK.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:50:22 03/20/2009
6 -- Design Name:
7 -- Module Name: VERSION_BLK - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
25 ---- Uncomment the following library declaration if instantiating
26 ---- any Xilinx primitives in this code.
27 --library UNISIM;
28 --use UNISIM.VComponents.all;
29 
30 entity VERSION_BLK is
31  Port ( version : out STD_LOGIC_VECTOR (7 downto 0));
32 end VERSION_BLK;
33 
34 architecture Behavioral of VERSION_BLK is
35 
36 begin
37 
38  version <= x"C2";
39 
40 end Behavioral;
41