otsdaq_prepmodernization  v2_04_01
BMG_STIM_GEN Entity Reference

Libraries

IEEE 
work 

Use Clauses

IEEE.STD_LOGIC_1164.all 
IEEE.STD_LOGIC_ARITH.all 
IEEE.STD_LOGIC_UNSIGNED.all 
IEEE.STD_LOGIC_MISC.all 
work.all 
work.BMG_TB_PKG.all 

Ports

CLKA   in STD_LOGIC
CLKB   in STD_LOGIC
TB_RST   in STD_LOGIC
ADDRA   out STD_LOGIC_VECTOR ( 9 downto 0 ) := ( others = > ' 0 ' )
DINA   out STD_LOGIC_VECTOR ( 31 downto 0 ) := ( others = > ' 0 ' )
WEA   out STD_LOGIC_VECTOR ( 0 downto 0 ) := ( others = > ' 0 ' )
ADDRB   out STD_LOGIC_VECTOR ( 9 downto 0 ) := ( others = > ' 0 ' )
CHECK_DATA   out STD_LOGIC := ' 0 '
CLK   in STD_LOGIC
RST   in STD_LOGIC

Detailed Description

Definition at line 121 of file bmg_stim_gen.vhd.


The documentation for this class was generated from the following files: