otsdaq_prepmodernization  v2_04_01
FADC_READ_CTRL.vhd
1 
2 ----------------------------------------------------------------------------------
3 -- Company:
4 -- Engineer:
5 --
6 -- Create Date: 12:22:00 07/28/2011
7 -- Design Name:
8 -- Module Name: FADC_READ_CTRL - Behavioral
9 -- Project Name:
10 -- Target Devices:
11 -- Tool versions:
12 -- Description:
13 --
14 -- Dependencies:
15 --
16 -- Revision:
17 -- Revision 0.01 - File Created
18 -- Additional Comments:
19 --
20 ----------------------------------------------------------------------------------
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_arith.all;
24 use IEEE.std_logic_unsigned.all;
25 use fadc_params_package.all;
26 
27 entity FADC_READ_CTRL is
28  Port ( mclk : in STD_LOGIC;
29  reset : in STD_LOGIC;
30  done : in STD_LOGIC;
31  rdata : in STD_LOGIC_VECTOR (63 downto 0);
32  waddr_rise : in STD_LOGIC_VECTOR (MEM_ADDR_SIZE-1 downto 0); --use as starting point
33  raddr : out STD_LOGIC_VECTOR (MEM_ADDR_SIZE-1 downto 0);
34  burst_we : out STD_LOGIC;
35  burst_end_packet : out STD_LOGIC;
36  burst_data : out STD_LOGIC_VECTOR (63 downto 0);
37  rdy_for_trig : out STD_LOGIC);
38 end FADC_READ_CTRL;
39 
40 architecture Behavioral of FADC_READ_CTRL is
41 
42  signal reading: STD_LOGIC;
43  signal rdy_for_trig_sig: STD_LOGIC;
44  signal delay_state: STD_LOGIC; --need to delay because writing 64 bits every MCLK overloads Ethernet
45  signal cnt: integer range 0 to 15; -- delay for ethernet to catch up
46  signal raddr_sig: STD_LOGIC_VECTOR (MEM_ADDR_SIZE-1 downto 0);
47  signal done_old : STD_LOGIC;
48 
49 begin
50 
51  --desc:
52  --rdy_for_trig = not (reset or reading).
53  --if reset, burst_we=0, burst_data=0xffffffffffffffff, reading=0.
54  --if rising edge of done, cnt=0, reading=1, burst_we=1, raddr= waddr_rise. --write all F's
55  --if reading = 1, cnt++, raddr--, burst_data = rdata. --first time data is from address = waddr_rise
56  --if raddr_sig = waddr_rise and reading_old = '1', reading = 0, burst_we=0.
57  --ADD BURST END PACKET!!!
58 
59 
60  raddr <= raddr_sig;
61  rdy_for_trig <= rdy_for_trig_sig;
62 
63  process(mclk)
64  begin
65 
66  if rising_edge(mclk) then
67 
68  burst_we <= '0';
69  burst_end_packet <= '0';
70  done_old <= done;
71 
72  if reset = '1' then
73  reading <= '0';
74  delay_state <= '0';
75  cnt <= 0;
76  burst_data <= (others => '1');
77  rdy_for_trig_sig <= '0';
78  else
79 
80  if reading = '1' and delay_state = '1' then -- DELAY STATE
81  cnt <= cnt + 1;
82 
83  if cnt = 3 then --give RAM a few clocks to stabilize read data
84  burst_data <= rdata; --first time data is from address = waddr_rise
85  --burst_data <= rdata(63 downto 24) & "0000" & waddr_rise & raddr_sig; --FOR DEBUGGING
86  burst_we <= '1'; --write fadc data
87  elsif cnt = 4 then --give 1 extra clock before changing raddr
88  raddr_sig <= raddr_sig - 1;
89  elsif cnt = BURST_WE_DELAY then --delay next write for some clocks
90  cnt <= 0;
91  delay_state <= '0';
92 
93  if raddr_sig = waddr_rise then -- gone all the way around.. (delay state is just used to avoid initial case)
94  reading <= '0';
95  burst_end_packet <= '1';
96  burst_data <= (others => '1');
97  end if;
98  end if;
99 
100  elsif reading = '1' then
101 
102  delay_state <= '1'; --got to delay state
103 
104  elsif rdy_for_trig_sig = '1' and reading = '0' and done_old = '0' and done = '1' then
105  reading <= '1';
106  burst_we <= '1'; --write all F's
107  raddr_sig <= waddr_rise;
108  burst_data <= (others => '1');
109  rdy_for_trig_sig <= '0';
110  delay_state <= '0';
111  cnt <= 0;
112  else
113  rdy_for_trig_sig <= '1';
114  end if;
115 
116 
117 
118  end if;
119 
120  end if;
121 
122  end process;
123 
124 end Behavioral;