1 --------------------------------------------------------------------------------
2 -- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
3 --------------------------------------------------------------------------------
6 -- /___/ \ / Vendor: Xilinx
7 -- \ \ \/ Version : 9.2.03i
8 -- \ \ Application : sch2vhdl
9 -- / / Filename : TOP_LEVEL.vhf
10 -- /___/ /\ Timestamp : 01/25/2008 15:27:05
14 --Command: C:\Xilinx_9_2\bin\nt\sch2vhdl.exe -intstyle ise -family virtex4 -flat -suppress -w C:/Xilinx_9_2/Projects/dig_mac_4GEL/TOP_LEVEL.sch TOP_LEVEL.vhf
15 --Design Name: TOP_LEVEL
18 -- This vhdl netlist is translated from an ECS schematic. It can be
19 -- synthesis and simulted, but it should not be modified.
23 use ieee.std_logic_1164.
ALL;
24 use ieee.numeric_std.
ALL;
26 use UNISIM.Vcomponents.
ALL;
29 port ( I : in (7 downto 0);
30 O : out (7 downto 0));
31 end OBUF8_MXILINX_TOP_LEVEL;
34 attribute IOSTANDARD : ;
35 attribute CAPACITANCE : ;
38 attribute BOX_TYPE : ;
43 attribute IOSTANDARD of OBUF : component is "DEFAULT";
44 attribute CAPACITANCE of OBUF : component is "DONT_CARE";
45 attribute SLEW of OBUF : component is "SLOW";
46 attribute DRIVE of OBUF : component is "12";
47 attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
87 use ieee.std_logic_1164.
ALL;
88 use ieee.numeric_std.
ALL;
90 use UNISIM.Vcomponents.
ALL;
93 port ( I : in (7 downto 0);
94 O : out (7 downto 0));
95 end IBUF8_MXILINX_TOP_LEVEL;
98 attribute IOSTANDARD : ;
99 attribute CAPACITANCE : ;
100 attribute BOX_TYPE : ;
105 attribute IOSTANDARD of IBUF : component is "DEFAULT";
106 attribute CAPACITANCE of IBUF : component is "DONT_CARE";
107 attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
147 use ieee.std_logic_1164.
ALL;
148 use ieee.numeric_std.
ALL;
150 use UNISIM.Vcomponents.
ALL;
153 port ( GMII_RXD_0 : in (7 downto 0);
159 PHY_TXD : out (7 downto 0);
165 attribute IOSTANDARD : ;
166 attribute CAPACITANCE : ;
169 attribute BOX_TYPE : ;
171 signal GMII_RXD_0_sig : (7 downto 0);
172 signal GMII_RX_CLK_0_sig : ;
173 signal GMII_RX_DV_0_sig : ;
174 signal GMII_RX_ER_0_sig : ;
175 signal GTX_CLK_0_sig : ;
176 signal PHY_TXD_sig : (7 downto 0);
177 signal PHY_TXEN_sig : ;
178 signal PHY_TXER_sig : ;
180 signal user_test_mode : ;
181 signal user_trigger : ;
182 signal XLXN_316 : (7 downto 0);
183 signal XLXN_317 : (10 downto 0);
184 signal XLXN_318 : (7 downto 0);
189 attribute IOSTANDARD of OBUF : component is "DEFAULT";
190 attribute CAPACITANCE of OBUF : component is "DONT_CARE";
191 attribute SLEW of OBUF : component is "SLOW";
192 attribute DRIVE of OBUF : component is "12";
193 attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
196 port ( addrs :
out (
7 downto 0);
197 size :
out (
10 downto 0);
198 data :
out (
7 downto 0));
205 attribute IOSTANDARD of IBUF : component is "DEFAULT";
206 attribute CAPACITANCE of IBUF : component is "DONT_CARE";
207 attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
210 port ( I :
in (
7 downto 0);
211 O :
out (
7 downto 0));
215 port ( I :
in (
7 downto 0);
216 O :
out (
7 downto 0));
223 attribute IOSTANDARD of IBUFG : component is "DEFAULT";
224 attribute CAPACITANCE of IBUFG : component is "DONT_CARE";
225 attribute BOX_TYPE of IBUFG : component is "BLACK_BOX";
227 component gigabit_ethernet_controller
228 port ( user_tx_data_in :
in (
7 downto 0);
229 user_tx_size_in :
in (
10 downto 0);
230 user_addrs :
in (
7 downto 0);
231 GMII_RXD :
in (
7 downto 0);
235 user_test_mode :
in ;
238 user_rx_size_out :
out (
10 downto 0);
243 user_rx_valid_out :
out ;
244 user_tx_enable_out :
out ;
245 user_rx_data_out :
out (
7 downto 0);
246 GMII_TXD :
out (
7 downto 0);
253 attribute BOX_TYPE of GND : component is "BLACK_BOX";
258 attribute BOX_TYPE of VCC : component is "BLACK_BOX";
260 attribute HU_SET of XLXI_180 : label is "XLXI_180_0";
261 attribute HU_SET of XLXI_195 : label is "XLXI_195_1";
264 port map (I =>reset_n,
268 port map (addrs
(7 downto 0)=>XLXN_316
(7 downto 0),
269 data
(7 downto 0)=>XLXN_318
(7 downto 0),
270 size
(10 downto 0)=>XLXN_317
(10 downto 0));
273 port map (I =>GMII_RX_DV_0,
274 O =>GMII_RX_DV_0_sig
);
277 port map (I =>GMII_RX_ER_0,
278 O =>GMII_RX_ER_0_sig
);
281 port map (I
(7 downto 0)=>GMII_RXD_0
(7 downto 0),
282 O
(7 downto 0)=>GMII_RXD_0_sig
(7 downto 0));
285 port map (I =>GTX_CLK_0_sig,
289 port map (I =>PHY_TXER_sig,
293 port map (I =>PHY_TXEN_sig,
297 port map (I
(7 downto 0)=>PHY_TXD_sig
(7 downto 0),
298 O
(7 downto 0)=>PHY_TXD
(7 downto 0));
301 port map (I =>GMII_RX_CLK_0,
302 O =>GMII_RX_CLK_0_sig
);
304 XLXI_274 : gigabit_ethernet_controller
305 port map (GMII_RXD
(7 downto 0)=>GMII_RXD_0_sig
(7 downto 0),
306 GMII_RX_CLK =>GMII_RX_CLK_0_sig ,
307 GMII_RX_DV =>GMII_RX_DV_0_sig,
308 GMII_RX_ER =>GMII_RX_ER_0_sig,
310 user_addrs
(7 downto 0)=>XLXN_316
(7 downto 0),
311 user_test_mode =>user_test_mode,
312 user_trigger =>user_trigger,
313 user_tx_data_in
(7 downto 0)=>XLXN_318
(7 downto 0),
314 user_tx_size_in
(10 downto 0)=>XLXN_317
(10 downto 0),
316 GMII_TXD
(7 downto 0)=>PHY_TXD_sig
(7 downto 0),
317 GMII_TX_EN =>PHY_TXEN_sig,
318 GMII_TX_ER =>PHY_TXER_sig,
319 GTX_CLK=>GTX_CLK_0_sig ,
321 user_rx_data_out =>
open,
322 user_rx_size_out =>
open,
323 user_rx_valid_out =>
open,
324 user_tx_enable_out =>
open);
327 port map (G =>user_test_mode
);
330 port map (P =>reset_n
);