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INFO_FIFO_0_exdes.vhd
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--------------------------------------------------------------------------------
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--
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-- FIFO Generator Core - core top file for implementation
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--
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--------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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--
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-- Filename: INFO_FIFO_0_exdes.vhd
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--
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-- Description:
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-- This is the FIFO core wrapper with BUFG instances for clock connections.
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
ieee.std_logic_arith.
all
;
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use
ieee.std_logic_unsigned.
all
;
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library
unisim
;
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use
unisim.vcomponents.
all
;
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--------------------------------------------------------------------------------
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-- Entity Declaration
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--------------------------------------------------------------------------------
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entity
INFO_FIFO_0_exdes
is
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PORT
(
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CLK
:
IN
std_logic
;
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SRST
:
IN
std_logic
;
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WR_EN
:
IN
std_logic
;
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RD_EN
:
IN
std_logic
;
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DIN
:
IN
std_logic_vector
(
16-1
DOWNTO
0
)
;
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DOUT
:
OUT
std_logic_vector
(
16-1
DOWNTO
0
)
;
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FULL
:
OUT
std_logic
;
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EMPTY
:
OUT
std_logic
)
;
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end
INFO_FIFO_0_exdes
;
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architecture
xilinx
of
INFO_FIFO_0_exdes
is
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signal
clk_i
:
std_logic
;
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component
INFO_FIFO_0
is
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PORT
(
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CLK :
IN
std_logic
;
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SRST :
IN
std_logic
;
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WR_EN :
IN
std_logic
;
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RD_EN :
IN
std_logic
;
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DIN :
IN
std_logic_vector
(
16-1
DOWNTO
0
);
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DOUT :
OUT
std_logic_vector
(
16-1
DOWNTO
0
);
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FULL :
OUT
std_logic
;
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EMPTY :
OUT
std_logic
);
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end
component
;
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begin
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clk_buf: bufg
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PORT
map
(
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i => CLK,
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o => clk_i
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)
;
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exdes_inst :
INFO_FIFO_0
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PORT
MAP
(
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CLK => clk_i,
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SRST => srst,
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WR_EN => wr_en,
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RD_EN => rd_en,
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DIN => din,
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DOUT => dout,
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FULL => full,
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EMPTY => empty
)
;
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end
xilinx
;
INFO_FIFO_0
Definition:
INFO_FIFO_0.vhd:43
INFO_FIFO_0_exdes
Definition:
INFO_FIFO_0_exdes.vhd:74
src
firmware
g-2
KickerControllerFirmware
ipcore_dir
INFO_FIFO_0
example_design
INFO_FIFO_0_exdes.vhd
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