otsdaq_prepmodernization  v2_04_01
IDELAY_CTRL.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:23:45 08/13/2008
6 -- Design Name:
7 -- Module Name: IDELAY_CTRL - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
25 ---- Uncomment the following library declaration if instantiating
26 ---- any Xilinx primitives in this code.
27 --library UNISIM;
28 --use UNISIM.VComponents.all;
29 
30 entity IDELAY_CTRL is
31  Port ( clk : in STD_LOGIC;
32  we : in STD_LOGIC;
33  data : in STD_LOGIC_VECTOR (7 downto 0);
34  del_ce : out STD_LOGIC;
35  del_inc : out STD_LOGIC;
36  del_rst : out STD_LOGIC);
37 end IDELAY_CTRL;
38 
39 architecture Behavioral of IDELAY_CTRL is
40 
41 begin
42 
43 
44 end Behavioral;
45