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IDELAY_CTRL.vhd
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
4
--
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-- Create Date: 10:23:45 08/13/2008
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-- Design Name:
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-- Module Name: IDELAY_CTRL - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library
IEEE
;
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use
IEEE.STD_LOGIC_1164.
ALL
;
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use
IEEE.STD_LOGIC_ARITH.
ALL
;
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use
IEEE.STD_LOGIC_UNSIGNED.
ALL
;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity
IDELAY_CTRL
is
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Port
(
clk
:
in
STD_LOGIC
;
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we
:
in
STD_LOGIC
;
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data
:
in
STD_LOGIC_VECTOR
(
7
downto
0
)
;
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del_ce
:
out
STD_LOGIC
;
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del_inc
:
out
STD_LOGIC
;
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del_rst
:
out
STD_LOGIC
)
;
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end
IDELAY_CTRL
;
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architecture
Behavioral
of
IDELAY_CTRL
is
40
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begin
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end
Behavioral
;
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IDELAY_CTRL
Definition:
IDELAY_CTRL.vhd:30
src
firmware
g-2
KickerControllerFirmware
GEL_CAPTAN
IDELAY_CTRL.vhd
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