otsdaq_prepmodernization  v2_04_01
burst_controller_sm.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : Burst Controller State Machine
4 -- Design : burst_controller
5 -- Author : Ryan Rivera
6 -- Company : FNAL
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : C:\Documents and Settings\rrivera\Desktop\CAPTAN_burst_controller_1\burst_controller\compile\burst_controller_sm.vhd
11 -- Generated : 04/08/11 10:17:01
12 -- From : C:/Documents and Settings/rrivera/Desktop/CAPTAN_burst_controller_1/burst_controller/src/burst_controller_sm.asf
13 -- By : FSM2VHDL ver. 5.0.7.2
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_arith.all;
24 use IEEE.std_logic_unsigned.all;
25 
27  port (
28  b_data_we: in STD_LOGIC;
29  b_end_burst: in STD_LOGIC;
30  b_end_packet: in STD_LOGIC;
31  burst_start: in STD_LOGIC;
32  burst_stop: in STD_LOGIC;
33  clk: in STD_LOGIC;
34  reset_n: in STD_LOGIC;
35  tx_data_full: in STD_LOGIC;
36  tx_info_full: in STD_LOGIC;
37  b_enable: out STD_LOGIC;
38  burst_done: out STD_LOGIC;
39  tx_data_we: out STD_LOGIC;
40  tx_info: out STD_LOGIC_VECTOR (15 downto 0);
41  tx_info_we: out STD_LOGIC);
42 end burst_controller_sm;
43 
44 architecture burst_controller_sm_arch of burst_controller_sm is
45 
46 constant max_packet_64_size: STD_LOGIC_VECTOR (7 downto 0) := x"B6"; -- 182;
47 -- diagram signals declarations
48 signal b_enable_sig: STD_LOGIC;
49 signal b_packet_64_size: STD_LOGIC_VECTOR (7 downto 0);
50 signal first_packet_sig: STD_LOGIC;
51 signal just_reset: STD_LOGIC;
52 signal reset_packet_size: STD_LOGIC;
53 
54 -- SYMBOLIC ENCODED state machine: Sreg0
55 type Sreg0_type is (
56  End_Burst, Wait_for_End, Inform_Decoder_Done, End_Packet, Reset_Size, Idle
57 );
58 -- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding
59 
60 signal Sreg0: Sreg0_type;
61 
62 begin
63 
64 -- concurrent signals assignments
65 
66 -- Diagram ACTION
67 tx_data_we <= b_enable_sig and b_data_we and (not tx_data_full) and (not tx_info_full);
68 -- don't allow writes when tx fifo is full
69 b_enable <= b_enable_sig;
70 -- proc_size counts the number of quad-words
71 -- in the current packet and saves the value
72 -- in b_packet_64_size.
73 proc_size: process(reset_n,clk,b_data_we)
74 begin
75  if reset_n = '0' then
76  b_packet_64_size <= (others => '0');
77  elsif rising_edge(clk) then
78  just_reset <= '0';
79  if b_enable_sig = '1' and b_data_we = '1' and tx_data_full = '0' and tx_info_full = '0' then
80  b_packet_64_size <= b_packet_64_size + 1;
81  if b_packet_64_size = max_packet_64_size or b_end_packet = '1' then -- include case where packet is ended at same time as b_we pulse
82  b_packet_64_size <= x"01";
83  -- start next packet (allows for burst to not use b_end_packet signal)
84  just_reset <= '1';
85  end if;
86  elsif b_enable_sig = '1' and b_end_packet = '1' then
87  b_packet_64_size <= (others => '0');
88  elsif just_reset = '0' and reset_packet_size = '1' then
89  b_packet_64_size <= (others => '0');
90  -- follow reset_packet_size flag, if didn't just reset
91  end if;
92  end if;
93 end process;
94 
95 ----------------------------------------------------------------------
96 -- Machine: Sreg0
97 ----------------------------------------------------------------------
98 Sreg0_machine: process (clk)
99 begin
100  if clk'event and clk = '1' then
101  if reset_n = '0' then
102  Sreg0 <= Idle;
103  -- Set default values for outputs, signals and variables
104  -- ...
105  tx_info <= (0 => '1',others => '0');
106  b_enable_sig <= '0';
107  burst_done <= '1';
108  tx_info_we <= '0';
109  first_packet_sig <= '1';
110  reset_packet_size <= '0';
111  else
112  -- Set default values for outputs, signals and variables
113  -- ...
114  case Sreg0 is
115  when End_Burst =>
116  Sreg0 <= Inform_Decoder_Done;
117  tx_info_we <= '0';
118  burst_done <= '1';
119  when Wait_for_End =>
120  if burst_stop = '1' or b_end_burst = '1' then
121  Sreg0 <= End_Burst;
122  tx_info(15 downto 8) <= b_packet_64_size;
123  tx_info(2 downto 0) <= "011";
124  tx_info_we <= '1';
125  b_enable_sig <= '0';
126  elsif b_end_packet = '1' or b_packet_64_size = max_packet_64_size then
127  Sreg0 <= End_Packet;
128  tx_info(15 downto 8) <= b_packet_64_size;
129  tx_info_we <= '1';
130  reset_packet_size <= '1';
131  end if;
132  when Inform_Decoder_Done =>
133  Sreg0 <= Reset_Size;
134  reset_packet_size <= '1';
135  when End_Packet =>
136  if b_end_packet='0' then
137  Sreg0 <= Wait_for_End;
138  if first_packet_sig = '1' then
139  tx_info(2 downto 0) <= "010";
140  first_packet_sig <= '0';
141  end if;
142  tx_info_we <= '0';
143  reset_packet_size <= '0';
144  end if;
145  when Reset_Size =>
146  Sreg0 <= Idle;
147  tx_info <= (0 => '1',others => '0');
148  b_enable_sig <= '0';
149  burst_done <= '1';
150  tx_info_we <= '0';
151  first_packet_sig <= '1';
152  reset_packet_size <= '0';
153  when Idle =>
154  if burst_start = '1' then
155  Sreg0 <= Wait_for_End;
156  b_enable_sig <= '1';
157  burst_done <= '0';
158  end if;
159 --vhdl_cover_off
160  when others =>
161  null;
162 --vhdl_cover_on
163  end case;
164  end if;
165  end if;
166 end process;
167 
168 end burst_controller_sm_arch;