otsdaq_prepmodernization  v2_04_01
GEC_RX_CTL_0.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : GEC_RX_CTL_0
4 -- Design : CAPTAN
5 -- Author : aprosser
6 -- Company : CD_CEPA_ESE
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : u:\CAPTAN\Data_Conversion_Board\CAPTAN\CAPTAN\compile\GEC_RX_CTL_0.vhd
11 -- Generated : 06/11/08 15:40:42
12 -- From : u:/CAPTAN/Data_Conversion_Board/CAPTAN/CAPTAN/src/GEC_RX_CTL_0.asf
13 -- By : FSM2VHDL ver. 5.0.0.9
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_arith.all;
24 use IEEE.std_logic_unsigned.all;
25 use params_package.all;
26 
27 entity gec_rx_ctl_0 is
28  port (
29  block_en: in STD_LOGIC;
30  clock: in STD_LOGIC;
31  data_fifo_full: in STD_LOGIC;
32  data_fifo_wrerr: in STD_LOGIC;
33  gec_user_crc_err: in STD_LOGIC;
34  gec_user_rx_size_out: in STD_LOGIC_VECTOR (10 downto 0);
35  gec_user_rx_valid_out: in STD_LOGIC;
36  reset_n: in STD_LOGIC;
37  crc_err_flag: out STD_LOGIC;
38  data_fifo_wren: out STD_LOGIC;
39  gec_rx_ctl_mux_sel: out STD_LOGIC;
40  gec_rx_ctl_stat_out: out STD_LOGIC_VECTOR (7 downto 0);
41  info_fifo_wr_data: out STD_LOGIC_VECTOR (15 downto 0);
42  info_fifo_wren: out STD_LOGIC;
43  rx_size_err_flag: out STD_LOGIC);
44 end gec_rx_ctl_0;
45 
46 architecture gec_rx_ctl_0 of GEC_RX_CTL_0 is
47 
48 -- diagram signals declarations
49 signal crc_err_reg: STD_LOGIC;
50 signal crc_loop_count: STD_LOGIC_VECTOR (4 downto 0);
51 signal gec_rx_data_count: STD_LOGIC_VECTOR (10 downto 0);
52 signal rx_data_count: STD_LOGIC_VECTOR (10 downto 0);
53 signal rx_size_err: STD_LOGIC;
54 signal stat_data_reg: STD_LOGIC_VECTOR (15 downto 0);
55 
56 -- SYMBOLIC ENCODED state machine: Sreg0
57 type Sreg0_type is (
58  idle, enabled, data_arrive, rcvdone, S1, update_info, S2
59 );
60 -- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding
61 
62 signal Sreg0: Sreg0_type;
63 
64 begin
65 
66 
67 ----------------------------------------------------------------------
68 -- Machine: Sreg0
69 ----------------------------------------------------------------------
70 Sreg0_machine: process (clock)
71 begin
72  if clock'event and clock = '1' then
73  if reset_n = '0' then
74  Sreg0 <= idle;
75  -- Set default values for outputs, signals and variables
76  -- ...
77 -- Initialize registers
78  rx_data_count <= v_11_0;
79  gec_rx_data_count <= v_11_0;
80  stat_data_reg <= v_16_0;
81  crc_err_reg <= '0';
82  rx_size_err <= '0';
83  crc_loop_count <= v_5_0;
84 -- Initialize error flag outputs
85  crc_err_flag <= '0';
86  rx_size_err_flag <= '0';
87 -- Initialize FIFO control outputs
88  data_fifo_wren <= '0';
89  info_fifo_wren <= '0';
90  info_fifo_wr_data <= v_16_0;
91 -- Initialize other control outputs
92  gec_rx_ctl_stat_out <= v_8_0;
93  gec_rx_ctl_mux_sel <= '0';
94 -- '0' points to GEC
95 -- '1' points to GEC_RX_CTL_0
96  else
97  -- Set default values for outputs, signals and variables
98  -- ...
99  case Sreg0 is
100  when idle =>
101  if block_en = '0' then
102  Sreg0 <= idle;
103  elsif block_en = '1' then
104  Sreg0 <= enabled;
105  end if;
106  when enabled =>
107  if gec_user_rx_valid_out = '0' then
108  Sreg0 <= enabled;
109  elsif gec_user_rx_valid_out = '1' then
110  Sreg0 <= data_arrive;
111  rx_data_count <= rx_data_count + v_11_1;
112  gec_rx_data_count <= gec_user_rx_size_out;
113  --data_fifo_wren <= '1';
114  -- Now driven by GEC user_rx_enable_out
115  -- and OR'd with data_fifo_wren
116  -- for last byte.
117  end if;
118  when data_arrive =>
119  if gec_user_rx_valid_out = '1' then
120  Sreg0 <= data_arrive;
121  rx_data_count <= rx_data_count + v_11_1;
122  -- Increment count with each received byte
123  -- data_fifo_wren <= '1';
124  -- Now driven by GEC user_rx_enable_out
125  -- and OR'd with data_fifo_wren
126  -- for last byte.
127  elsif gec_user_rx_valid_out = '0' then
128  Sreg0 <= update_info;
129  if (gec_user_crc_err = '1') then
130  crc_err_reg <= '1';
131  end if;
132  if (gec_rx_data_count /= rx_data_count) then
133  rx_size_err <= '1';
134  end if;
135  rx_data_count <= rx_data_count + v_11_1;
136  -- Add a count for the status byte
137  -- to be sent back to the PC
138  data_fifo_wren <= '0';
139  end if;
140  when rcvdone =>
141  if block_en = '0' then
142  Sreg0 <= idle;
143  elsif block_en = '1' then
144  Sreg0 <= enabled;
145  end if;
146  when S1 =>
147  Sreg0 <= S2;
148  info_fifo_wren <= '0';
149  gec_rx_ctl_stat_out(1 downto 0) <= rx_size_err & crc_err_reg;
150  data_fifo_wren <= '1';
151  when update_info =>
152  if (crc_loop_count = v_5_22) or
153  (gec_user_crc_err = '1') or
154  (crc_err_reg = '1') then
155  Sreg0 <= S1;
156  gec_rx_ctl_mux_sel <= '1';
157  -- Set data mux to point to receive controller
158  -- (instead of GEC) to load extra info to send
159  -- back to PC
160  if (gec_user_crc_err = '0') then -- this is a spoof
161  crc_err_reg <= '1';
162  end if;
163  info_fifo_wr_data(10 downto 0) <= rx_data_count;
164  info_fifo_wren <= '1';
165  elsif (crc_loop_count < v_5_22) and
166  (gec_user_crc_err = '0') then
167  Sreg0 <= update_info;
168  crc_loop_count <= crc_loop_count + v_5_1;
169  end if;
170  when S2 =>
171  Sreg0 <= rcvdone;
172  rx_data_count <= v_11_0;
173  stat_data_reg <= v_16_0;
174  crc_err_reg <= '0';
175  crc_err_flag <= '0';
176  crc_loop_count <= v_5_0;
177  rx_size_err_flag <= '0';
178  data_fifo_wren <= '0';
179  info_fifo_wren <= '0';
180  info_fifo_wr_data <= v_16_0;
181  gec_rx_ctl_stat_out <= v_8_0;
182  gec_rx_ctl_mux_sel <= '0';
183  -- '0' points to GEC
184  -- '1' points to GEC_RX_CTL_0
185  when others =>
186  null;
187  end case;
188  end if;
189  end if;
190 end process;
191 
192 end GEC_RX_CTL_0;