otsdaq_components  v2_04_01
FSSROtsFirmware.cc
1 #include "otsdaq-components/DAQHardware/FSSROtsFirmware.h"
2 
3 //#include "otsdaq-components/DAQHardware/FSSRFirmwareDefinitions.h"
4 //#include "otsdaq-core/BitManipulator/BitManipulator.h"
5 //#include "otsdaq-components/DetectorHardware/FSSRROCDefinitions.h"
6 
7 #include "otsdaq-components/DAQHardware/FrontEndFirmwareBase.h"
8 #include "otsdaq-components/DAQHardware/OtsUDPFirmwareCore.h"
9 #include "otsdaq-components/DAQHardware/PurdueFirmwareCore.h"
10 
11 #include <arpa/inet.h>
12 #include <netinet/in.h>
13 #include <sys/socket.h>
14 #include "otsdaq-core/Macros/CoutMacros.h"
15 #include "otsdaq-core/MessageFacility/MessageFacility.h"
16 
17 #include <cstdlib>
18 #include <iostream>
19 
20 using namespace ots;
21 
22 //========================================================================================================================
23 FSSROtsFirmware::FSSROtsFirmware(std::string communicationFirmwareType,
24  unsigned int communicationFirmwareVersion,
25  unsigned int applicationFirmwareVersion)
26  : FSSRFirmwareBase(communicationFirmwareType,
27  communicationFirmwareVersion,
28  applicationFirmwareVersion)
29 {
30 }
31 // //choose: OtsUDPFirmwareCore or PurdueFirmwareCore
32 // if(communicationFirmwareType == FrontEndFirmwareBase::PURDUE_CORE_FIRMWARE_NAME)
33 // communicationFirmwareInstance_ = new
34 // PurdueFirmwareCore(communicationFirmwareVersion); if(communicationFirmwareType ==
35 // FrontEndFirmwareBase::OTS_CORE_FIRMWARE_NAME) communicationFirmwareInstance_ =
36 // new OtsUDPFirmwareCore(communicationFirmwareVersion); else
37 // {
38 // __SS__ << "Unknown firmware type choice: " << choice << std::endl;
39 // __COUT_ERR__ << ss.str();
40 // __SS_THROW__;
41 // }
42 //
43 //
44 // //make protocol a class member
45 // //protocolInstance_ = new OtsFirmwareCore(version);//AUG-17-2017 RAR dissociated
46 // because function calls are entirely independent from PURDUE firmware calls //
48 // //assert(protocolInstance_ != NULL);
49 // //returns either new OtsUDPFirmware or new PurdueFirmwareCore,
50 // //now we can call write/read etc with protocol->write, protocol->read, etc
51 //}
52 
53 //========================================================================================================================
54 FSSROtsFirmware::~FSSROtsFirmware(void)
55 {
56  // delete protocolInstance_;
57  // protocolInstance_ = NULL;
58 }
59 
60 //========================================================================================================================
61 void FSSROtsFirmware::init(void) {}
62 
63 /*
64 //========================================================================================================================
65 std::string FSSROtsFirmware::configureClocks(std::string source, double frequency)
66 {
67  std::cout << __COUT_HDR_FL__ << "Writing Clock configuration!" << std::endl;
68 
69  std::string buffer;
70  //NoNeedNowwrite(buffer, ETHIO_DESTINATION_PORT, 0x0000b798); // Listen port for
71 ethio stuff
72 
73  setPacketSizeStripCSR(6);
74  setExternalBCOClockSourceStripCSR(source); //(source)
75  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); // Reset CSR -
76 reset trigger counter, external 27 MHz clock
77 
78  resetDCMStripCSR(true);
79  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); // Set reset to
80 DCM
81 
82  resetDCMStripCSR(false);
83  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); // Clear reset
84 to DCM
85 
86  ;
87  //FIXME? Does Nothing RAR Aug 2017// OtsUDPFirmwareCore::waitClear(buffer, STRIP_CSR,
88 waitDCMResetStripCSR()); // Wait for DCM to lock
89 
90  OtsUDPFirmwareCore::write(buffer, STRIP_TRIM_CSR, 0x00002000); // MCLKB edge for
91 channel 5 // was 0x00002000
92 
93  setFrequencyFromClockState(buffer, frequency);
94  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
95 
96  resetDCMStripCSR(true);
97  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
98 
99  resetDCMStripCSR(false);
100  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
101 
102  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer, STRIP_CSR,
103 waitDCMResetStripCSR()); // Wait for DCM to lock std::cout << __COUT_HDR_FL__ <<
104 "stripCSRRegisterValue :" << std::hex << stripCSRRegisterValue_ << std::dec << std::endl;
105 
106  return buffer;
107 }
108 
109 //========================================================================================================================
110 std::string FSSROtsFirmware::resetDetector(int channel)
111 {
112  std::cout << __COUT_HDR_FL__ << "Resetting detector!" << std::endl;
113  std::string buffer;
114  if (channel == -1)//reset all channels
115  {
116  //write(buffer,STRIP_RESET,0xd000003f); // Issue reset
117  OtsUDPFirmwareCore::write(buffer, STRIP_RESET, 0xf000003f); // Issue reset // was
118 0xf000003f
119  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer,
120 STRIP_RESET, 0xf0000000); // Wait for reset to complete // was 0xf0000000 } else
121  {
122  OtsUDPFirmwareCore::write(buffer, STRIP_RESET, 0xf000003f); // Issue reset
123  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer,
124 STRIP_RESET, 0xf0000000); // Wait for reset to complete
125  }
126 
127  return buffer;
128 }
129 
130 //========================================================================================================================
131 std::string FSSROtsFirmware::enableTrigger(void)
132 {
133  std::string buffer;
134  std::cout << __COUT_HDR_FL__ << "Enabling Trigger!!!" << std::endl;
135  std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue in :" << std::hex <<
136 stripCSRRegisterValue_ << std::dec << std::endl;
137 
138  setHaltStripCSR(1);//WARNING THIS IS CLEARED BY THE MASTER BUT IF THERE IS NO MASTER
139 NOTHING WORKS UNLESS THE BIT IS UNSET
140  //setHaltStripCSR(0);//WARNING THIS IS CLEARED BY THE MASTER BUT IF THERE IS NO MASTER
141 NOTHING WORKS UNLESS THE BIT IS UNSET sendTriggerDataStripCSR(true);
142  sendTriggerNumberStripCSR(true);
143  sendBCOStripCSR(true);
144  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
145 
146  stripTriggerCSRRegisterValue_ = 0;
147  BCOOffset(4);
148  OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_CSR, stripTriggerCSRRegisterValue_); //
149 BCO offset // was 0x00000004
150 
151  // write(buffer,STRIP_TRIG_INPUT_0,0x1f060040); // FSSR GOTHIT trigger input -
152 timed in for the 27 MHz external clock
153  // write(buffer,STRIP_TRIG_INPUT_3,0x3f874040); // Unbiased trigger input +
154 external trigger
155 
156  configureStripTriggerUnbiased(buffer);
157 
158  configureTriggerInputs(buffer);
159 
160  //FIXME for IP .36 the number to set is 0x20401000
161 
162  if (OtsUDPFirmwareCore::version_ == 1)
163  OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_INPUT_3, 0x20401000); // Turn on
164 streaming hits along with BCO data else if (OtsUDPFirmwareCore::version_ == 2)
165  OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_INPUT_3, 0x20301000); // Turn on
166 streaming hits along with BCO data else
167  {
168  __SS__ << "what version is this?" <<
169  OtsUDPFirmwareCore::version_ << std::endl;
170  __COUT_ERR__ << "\n" << ss.str();
171  __SS_THROW__;
172  }
173  std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue out:" << std::hex <<
174 stripCSRRegisterValue_ << std::dec << std::endl; std::cout << __COUT_HDR_FL__ << "Done
175 enabling Trigger!!!" << std::endl;
176 
177  return buffer;
178 }
179 
180 //========================================================================================================================
181 void FSSROtsFirmware::readBurstDestinationIP(std::string& buffer)
182 {
183  OtsUDPFirmwareCore::read(buffer, (uint64_t)0x0000000100000006);
184 }
185 
186 //========================================================================================================================
187 void FSSROtsFirmware::readBurstDestinationMAC(std::string& buffer)
188 {
189  OtsUDPFirmwareCore::read(buffer, (uint64_t)0x0000000100000007);
190 }
191 
192 //========================================================================================================================
193 void FSSROtsFirmware::readBurstDestinationPort(std::string& buffer)
194 {
195  OtsUDPFirmwareCore::read(buffer, (uint64_t)0x0000000100000008);
196 }
197 
198 //========================================================================================================================
199 void FSSROtsFirmware::writeBurstDestinationIP(std::string& buffer, const uint64_t value)
200 {
201  OtsUDPFirmwareCore::write(buffer, (uint64_t)0x0000000100000006, value);
202 }
203 
204 //========================================================================================================================
205 void FSSROtsFirmware::writeBurstDestinationMAC(std::string& buffer, const uint64_t value)
206 {
207  OtsUDPFirmwareCore::write(buffer, (uint64_t)0x0000000100000007, value);
208 }
209 
210 //========================================================================================================================
211 void FSSROtsFirmware::writeBurstDestinationPort(std::string& buffer, const uint64_t value)
212 {
213  OtsUDPFirmwareCore::write(buffer, 0x0000000100000008, value);
214 }
215 
216 //========================================================================================================================
217 std::string FSSROtsFirmware::resetBCO(void)
218 {
219  std::cout << __COUT_HDR_FL__ << "Reset BCO!!!" << std::endl;
220  std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue in :" << std::hex <<
221 stripCSRRegisterValue_ << std::dec << std::endl; std::string buffer;
222 
223  resetTriggerCounterStripCSR(buffer);
224  //write(buffer, STRIP_CSR, stripCSRRegisterValue_);//the write is done in the reset
225  std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue :" << std::hex <<
226 stripCSRRegisterValue_ << std::dec << std::endl;
227 
228  //msg->Write(STRIP_SC_CSR,0x90000b95|(chmask<<16));
229  //write(buffer,STRIP_SC_CSR,0x900f0b95);// This is the <SCR,set> command with the bit
230 set to sync SHIFT with BCO=0.
231 
232 
233  enableBCOStripCSR(true);
234  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
235  std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue out:" << std::hex <<
236 stripCSRRegisterValue_ << std::dec << std::endl; std::cout << __COUT_HDR_FL__ << "Done
237 reset BCO!!!" << std::endl;
238 
239  return buffer;
240 }
241 
242 //========================================================================================================================
243 std::string FSSROtsFirmware::startStream(bool channel0, bool channel1, bool channel2, bool
244 channel3, bool channel4, bool channel5)
245 {
246  std::cout << __COUT_HDR_FL__ << "Start Stream!" << std::endl;
247  std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue in:" << std::hex <<
248 stripCSRRegisterValue_ << std::dec << std::endl; std::string buffer;
249 
250  std::cout << __COUT_HDR_FL__ << " channel0 " << channel0 << " channel1 " << channel1
251 << " channel2 " << channel2 << " channel3 " << channel3 << " channel4 " << channel4 << "
252 channel5 " << channel5 << std::endl;
253 
254  enableChannelsStripCSR(channel0, channel1, channel2, channel3, channel4, channel5);
255  // if (version_ == 1)
256  // enableChannelsStripCSR(true, true, true, true, false, false);
257  // else if (version_ == 2)
258  // enableChannelsStripCSR(true, true, true, true, true, true);
259 
260  enableStreamStripCSR(true); // Turn on streaming hits along with BCO data // was
261 0x0f000f30 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
262 
263  std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue out:" << std::hex <<
264 stripCSRRegisterValue_ << std::dec << std::endl; std::cout << __COUT_HDR_FL__ << "Done
265 start Stream!" << std::endl;
266 
267  return buffer;
268 }
269 
270 //========================================================================================================================
271 std::string FSSROtsFirmware::stopStream(void)
272 {
273  std::string buffer;
274  enableChannelsStripCSR(false, false, false, false, false, false);
275  enableStreamStripCSR(false);
276  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
277  return buffer;
278 }
279 
280 //========================================================================================================================
281 void FSSROtsFirmware::makeDACSequence(FirmwareSequence<uint64_t>& sequence,
282  unsigned int channel, const ROCStream& rocStream)
283 {
284  const ROCDACs& rocDACs = rocStream.getROCDACs();
285  for (DACList::const_iterator it = rocDACs.getDACList().begin(); it
286  != rocDACs.getDACList().end(); it++)
287  {
288  //if(it->first != "SendData" && it->first != "RejectHits") continue;
289  uint64_t data = FSSRROCDefinitions::makeDACWriteCommand(
290  rocStream.getFEWROCAddress(), it->first, it->second.second);
291  sequence.pushBack(ChannelFIFOAddress[channel], data);
292  sequence.pushBack(ChannelFIFOAddress[channel],
293  BitManipulator::insertBits(data, (uint64_t) 0x48, 56, 8));
294  //set WRITE
295  sequence.pushBack(ChannelFIFOAddress[channel],
296  BitManipulator::insertBits(data, (uint64_t) 1, 60, 1));
297  //clr WRITE
298  sequence.pushBack(ChannelFIFOAddress[channel],
299  BitManipulator::insertBits(data, (uint64_t) 0, 60, 1));
300  //clr TALK
301  sequence.pushBack(ChannelFIFOAddress[channel],
302  BitManipulator::insertBits(data, (uint64_t) 0, 62, 1));
303  sequence.pushBack(ChannelFIFOAddress[channel],
304  BitManipulator::insertBits(data, (uint64_t) 0x40, 56, 8));
305  //break;
306  }
307 }
308 
309 //========================================================================================================================
310 void FSSROtsFirmware::makeDACSequence(FirmwareSequence<uint32_t>& sequence,
311  unsigned int channel, const ROCStream& rocStream)
312 {
313  const ROCDACs& rocDACs = rocStream.getROCDACs();
314  for (DACList::const_iterator it = rocDACs.getDACList().begin(); it
315  != rocDACs.getDACList().end(); it++)
316  {
317  //RYAN
318  //if(it->first != "SendData" && it->first != "RejectHits") continue;
319  uint64_t data =
320 FSSRROCDefinitions::makeDACWriteCommand(rocStream.getFEWROCAddress(), it->first,
321 it->second.second);
322  //sequence.pushBack(ChannelFIFOAddress[channel], data);
323  //sequence.pushBack(ChannelFIFOAddress[channel],
324 BitManipulator::insertBits(data,(uint32_t)0x48,56,8));
325  //set WRITE
326  //sequence.pushBack(ChannelFIFOAddress[channel],
327 BitManipulator::insertBits(data,(uint32_t)1,60,1));
328  //clr WRITE
329  //sequence.pushBack(ChannelFIFOAddress[channel],
330 BitManipulator::insertBits(data,(uint32_t)0,60,1));
331  //clr TALK
332  //sequence.pushBack(ChannelFIFOAddress[channel],
333 BitManipulator::insertBits(data,(uint32_t)0,62,1));
334  //sequence.pushBack(ChannelFIFOAddress[channel],
335 BitManipulator::insertBits(data,(uint32_t)0x40,56,8));
336 
337 
338  //if(it->first != "SendData" && it->first != "RejectHits") continue;
339  uint32_t data = FSSRROCDefinitions::makeDACWriteHeader(
340  rocStream.getFEWROCAddress(), it->first);
341  //Insert channel
342  BitManipulator::insertBits(data, 1, 16 + channel, 1);
343  sequence.pushBack(ChannelFIFOAddress[channel], it->second.second);
344  std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " << it->first
345 << " value: "
346  << it->second.second << std::hex << " -> Data: " << data << std::dec
347  << std::endl;
348  sequence.pushBack(STRIP_SC_CSR, data);
349  }
350 }
351 
352 //========================================================================================================================
353 void FSSROtsFirmware::makeDACBuffer(std::string& buffer,
354  unsigned int channel, const ROCStream& rocStream)
355 {
356  std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Channel: " << channel <<
357 std::endl; const ROCDACs& rocDACs = rocStream.getROCDACs(); for (DACList::const_iterator
358 it = rocDACs.getDACList().begin(); it != rocDACs.getDACList().end(); it++)
359  {
360  std::string bufferElement;
361  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(bufferElement,
362 STRIP_SC_CSR, 0x80000000); uint32_t registerHeader = 0;
363  //FIXME This must go in the FSSRROCDefinitions stuff
364  if (it->first != "RejectHits" && it->first != "SendData")
365  {
366  OtsUDPFirmwareCore::write(bufferElement, ChannelFIFOAddress[channel],
367 it->second.second); registerHeader = FSSRROCDefinitions::makeDACWriteHeader(
368  rocStream.getFEWROCAddress(), it->first);
369  //std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " <<
370 it->first << " value: " << it->second.second << std::hex << " -> Data: " << registerHeader
371 << std::dec << std::endl;
372  //Insert channel
373  BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1);
374  }
375  else
376  {
377  if (it->second.second == 1 || it->second.second == 2)
378  {
379  registerHeader = FSSRROCDefinitions::makeDACSetHeader(
380  rocStream.getFEWROCAddress(), it->first);
381  //Insert channel
382  BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1);
383  }
384  else if (it->second.second == 0 || it->second.second == 5)
385  {
386  registerHeader = FSSRROCDefinitions::makeDACResetHeader(
387  rocStream.getFEWROCAddress(), it->first);
388  //Insert channel
389  BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1);
390  }
391  else
392  std::cout << __COUT_HDR_FL__ << "Register value for : " << it->first
393  << " doesn't have a value I expect -> value = "
394  << it->second.second << std::endl;
395 
396  }
397  //std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " << it->first
398 << " value: " << it->second.second << std::hex << " -> Data: " << registerHeader <<
399 std::dec << std::endl; OtsUDPFirmwareCore::write(bufferElement, STRIP_SC_CSR,
400 registerHeader);
401  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(bufferElement,
402 STRIP_SC_CSR, 0x80000000);
403 
404  //buffer.push_back(bufferElement);
405  buffer += bufferElement;
406  //break;
407  }
408 }
409 
410 //========================================================================================================================
411 void FSSROtsFirmware:: makeDACBuffer(std::vector<std::string>& buffer, unsigned int
412 channel, const ROCStream& rocStream)
413 {
414 
415  std::cout << __COUT_HDR_FL__ << "\tMaking DAC Buffer" << std::endl;
416 
417  int limitCount = 0;
418  unsigned int singleVectorCount = 0;
419 
420  std::string alternateBuffer;
421 
422  std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Channel: " << channel <<
423 std::endl; const ROCDACs& rocDACs = rocStream.getROCDACs();
424  //std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Number of DACs: " <<
425 rocDACs.getDACList().size() << std::endl; std::string bufferElement; for
426 (DACList::const_iterator it = rocDACs.getDACList().begin(); it !=
427 rocDACs.getDACList().end(); it++)
428  {
429  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(bufferElement,
430 STRIP_SC_CSR, 0x80000000); uint32_t registerHeader = 0;
431  //FIXME This must go in the FSSRROCDefinitions stuff
432  if (it->first != "RejectHits" && it->first != "SendData")
433  {
434  OtsUDPFirmwareCore::write(bufferElement, ChannelFIFOAddress[channel],
435 it->second.second); registerHeader = FSSRROCDefinitions::makeDACWriteHeader(
436  rocStream.getFEWROCAddress(), it->first);
437  std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " <<
438 it->first << " value: " << it->second.second << std::hex << " -> Data: " << registerHeader
439 << std::dec << std::endl;
440  //Insert channel
441  BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1);
442  }
443  else
444  {
445  if (it->second.second == 1 || it->second.second == 2)
446  {
447  registerHeader = FSSRROCDefinitions::makeDACSetHeader(
448  rocStream.getFEWROCAddress(), it->first);
449  //Insert channel
450  BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1);
451  }
452  else if (it->second.second == 0 || it->second.second == 5)
453  {
454  registerHeader = FSSRROCDefinitions::makeDACResetHeader(
455  rocStream.getFEWROCAddress(), it->first);
456  //Insert channel
457  BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1);
458  }
459  else
460  std::cout << __COUT_HDR_FL__ << "Register value for : " << it->first
461  << " doesn't have a value I expect -> value = "
462  << it->second.second << std::endl;
463 
464  }
465  //std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " << it->first
466 << " value: " << it->second.second << std::hex << " -> Data: " << registerHeader <<
467 std::dec << std::endl; OtsUDPFirmwareCore::write(bufferElement, STRIP_SC_CSR,
468 registerHeader);
469  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(bufferElement,
470 STRIP_SC_CSR, 0x80000000);
471 
472  //alternateBuffer += bufferElement;
473  limitCount++;
474  singleVectorCount++;
475 
476  if (limitCount == STIB_DAC_WRITE_MAX)
477  {
478  std::cout << __COUT_HDR_FL__ << "\tBuffer lenght:" << bufferElement.size() <<
479 std::endl; buffer.push_back(bufferElement); limitCount = 0; bufferElement.clear();
480  }
481  else if (singleVectorCount == rocDACs.getDACList().size()) //case for imcomplete
482 packet
483  {
484  buffer.push_back(bufferElement);
485  }
486 
487  //buffer.push_back(bufferElement);
488  //break;
489  }
490  std::cout << __COUT_HDR_FL__ << "\tDone making DAC Buffer" << std::endl;
491 
492 }
493 
494 //========================================================================================================================
495 void FSSROtsFirmware::makeMaskBuffer(std::string& buffer, unsigned int channel,
496  const ROCStream& rocStream)
497 {
498  std::cout << __COUT_HDR_FL__ << "Making mask! " << std::endl;
499  makeMaskBuffer(buffer, channel, rocStream, "Kill");
500  // makeMaskSequence(buffer, channel, rocStream, "Inject");
501 }
502 
503 //========================================================================================================================
504 void FSSROtsFirmware::makeMaskBuffer(std::string& buffer, unsigned int channel, const
505 ROCStream& rocStream, const std::string& registerName)
506 {
507  std::cout << __COUT_HDR_FL__ << "\tMaking mask! " << std::endl;
508  int chipId = rocStream.getFEWROCAddress();
509  std::string mask = rocStream.getROCMask();
510  std::cout << __COUT_HDR_FL__ << "\tMask length: " << mask.length() << std::endl;
511 
512  unsigned int data[4] = { 0, 0, 0, 0 };
513 
514  char val;
515  //int j = 0;
516  for (unsigned int d = 0; d < 4; d++)
517  { //d goes from 0 to 4. 4 bytes
518  //std::cout << __COUT_HDR_FL__ << "---------------------" << d <<
519 "-------------------" << std::endl; for (unsigned int m = 0; m < 8 * 4; m++) { //m goes
520 from 0 to 31, since each byte has 8 bits, there are 32 bits val = mask[(8 * 4 * d) + m];
521 //assigns to val the value of the corresponding bit. 0-31, 32-63, 64-95, 96-127. it goes
522 through each of the 128 bits
523  //std::cout << __COUT_HDR_FL__ << "---------------------" << j++ << std::endl;
524  //std::cout << __COUT_HDR_FL__ << "data[" << d << "] before: " << std::hex <<
525 data[d] << std::dec << std::endl; data[d] |= (unsigned int) atoi(&val) << (8 * 4 - 1 - m);
526  //std::cout << __COUT_HDR_FL__ << "(unsigned int) atoi(&val): " << (unsigned
527 int) atoi(&val) << std::endl;
528  //std::cout << __COUT_HDR_FL__ << "data[" << d << "] after: " << std::hex <<
529 data[d] << std::dec << std::endl;
530  //std::cout << __COUT_HDR_FL__ << std::hex << "D: " << data[d] << " Val: " <<
531 (unsigned int)atoi(&val) << " index: " << std::dec << (8*4-1-m) << " bit: " <<
532 mask[(8*4*d)+m] << std::dec << std::endl;
533  }
534  //
535  }
536 
537  int i, ierr;
538  unsigned int w;
539  unsigned char len = 4;
540  unsigned char addr = 17;//Kill
541  unsigned char bitMask = 1 << channel;
542  unsigned char inst = WRITE;
543 
544  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer,
545 STRIP_SC_CSR, 0x80000000);
546 
547  for (i = 0; i < 4; i++)
548  //write(buffer, STRIP_SCI + 4 * i, data[i]);
549  OtsUDPFirmwareCore::write(buffer, STRIP_SCI + 4 * (4 - i - 1), data[i]);
550 
551  w = 0x80000000 | (len << 24) | (bitMask << 16) | (inst << 10) | (addr << 5) | chipId;
552 
553  //ierr = OtsUDPFirmwareCore::write(buffer, STRIP_SC_CSR, w);
554  OtsUDPFirmwareCore::write(buffer, STRIP_SC_CSR, w);
555 
556  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer,
557 STRIP_SC_CSR, 0x80000000);
558 }
559 
560 //========================================================================================================================
561 void FSSROtsFirmware::makeMaskSequence(FirmwareSequence<uint64_t>& sequence,
562  unsigned int channel, const ROCStream& rocStream)
563 {
564  std::cout << __COUT_HDR_FL__ << "Making mask! " << std::endl;
565  makeMaskSequence(sequence, channel, rocStream, "Kill");
566  // makeMaskSequence(sequence, channel, rocStream, "Inject");
567 }
568 
569 //========================================================================================================================
570 void FSSROtsFirmware::makeMaskSequence(FirmwareSequence<uint32_t>& sequence,
571  unsigned int channel, const ROCStream& rocStream)
572 {
573  std::cout << __COUT_HDR_FL__ << "Making mask! " << std::endl;
574  makeMaskSequence(sequence, channel, rocStream, "Kill");
575  // makeMaskSequence(channel,rocStream,sequence,"Inject");
576 }
577 
578 //========================================================================================================================
579 void FSSROtsFirmware::makeMaskSequence(FirmwareSequence<uint64_t>& sequence,
580  unsigned int channel, const ROCStream& rocStream,
581  const std::string& registerName)
582 {
583  int chipId = rocStream.getFEWROCAddress();//9, 14 or 21 bcast
584  std::string mask = rocStream.getROCMask();
585  std::cout << __COUT_HDR_FL__ << "Mask length: " << mask.length() << std::endl;
586 
587  uint64_t uInt64Data = 0;
588  std::string stringData = "";
589 
590  //have to manually set every bit for mask writes.
591  //reset fifo
592  //download every bit (shift_in and shift_ctrl) to fifo (setup muxes and control lines)
593  //configure muxes for readout
594  //commence readout
595 
596  //FIFO Controls - byte 5 (7:0)
597  //7 - FIFO Clock
598  //6 - Shift Ctrl bit
599  //MASK_CELL_H - Shift In bit
600  //MUX Controls - byte 0 (7:0)
601  //7 - Read En/Output MUX sel (1 for masks)
602  //1 - Write En for mux
603  //0 - Reset Fifo
604 
605  //reset fifo
606  BitManipulator::insertBits(uInt64Data, 0x1, 56, 8);
607  sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
608 
609  //configure fifo for write
610  BitManipulator::insertBits(uInt64Data, 0x2, 56, 8);
611  sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
612 
613  //Download every bit (shift_in and shift_control) to fifo (setup muxes and control
614 lines)
615  //Bit 7 of data is FIFO clock, bit 6 is shift_control, bit 5 is shift_in
616  //start bits (ctrl 0, data 0 => ctrl 1, data 0)
617 
618  BitManipulator::insertBits(uInt64Data, 0x40, 16, 8);//(0<<7) | (1<<6) | (0<<5)
619  sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
620  BitManipulator::insertBits(uInt64Data, 0xc0, 16, 8);//(1<<7) | (1<<6) | (0<<5) ->
621 clock the data in the fifo sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
622 
623  stringData = FSSRROCDefinitions::makeMaskWriteCommand(chipId,
624  registerName, mask);
625 
626  uint8_t data;
627  for (unsigned int s = 0; s < stringData.length(); s++)
628  for (int b = 8 - 1; b >= 0 && (s * 8 + 8 - b < 13 + 128); b--)
629  {
630  //std::cout << __COUT_HDR_FL__ << "S: " << s << " val: " <<
631 stringData.data()[s] << " b: " << b << " bit: " << ((stringData.data()[s]>>b)&1) <<
632 std::endl; data = 0x40 | (((stringData.data()[s] >> b) & 1) << 5);
633  BitManipulator::insertBits(uInt64Data, (uint64_t) data, 16, 8);
634  sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
635  data |= 0x80;
636  BitManipulator::insertBits(uInt64Data, (uint64_t) data, 16, 8);
637  sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
638  }
639 
640  //reset Shift Control
641  BitManipulator::insertBits(uInt64Data, 0x0, 16, 8);
642  sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
643  BitManipulator::insertBits(uInt64Data, 0x80, 16, 8);
644  sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
645 
646  //configure muxes for readout
647  BitManipulator::insertBits(uInt64Data, 0x0, 56, 8);
648  sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
649 
650  //commence readout
651  BitManipulator::insertBits(uInt64Data, 0x80, 56, 8);
652  sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data);
653 
654 }
655 
656 //========================================================================================================================
657 void FSSROtsFirmware::makeMaskSequence(FirmwareSequence<uint32_t>& sequence,
658  unsigned int channel, const ROCStream& rocStream,
659  const std::string& registerName)
660 {}
661 
662 //========================================================================================================================
663 std::string FSSROtsFirmware::readCSRRegister()
664 {
665  std::string buffer;
666  OtsUDPFirmwareCore::read(buffer,STRIP_CSR);
667  return buffer;
668 }
669 
670 //========================================================================================================================
671 void FSSROtsFirmware::setFrequencyFromClockState(std::string& buffer, double frequency)
672 {
673  std::cout << __COUT_HDR_FL__ << "Setting up clock frequency!!!" << std::endl;
674 
675  int quotient;
676  int numerator;
677  int denominator;
678  double realClockFrequency;
679 
680  if (BitManipulator::readBits(stripCSRRegisterValue_, 17, 1) == 1) //if fastBCO is
681 enabled quotient = 4; else //normal cases quotient = 8;
682 
683  if (isClockStateExternal()) //base freq: 54MHz
684  {
685  realClockFrequency = EXTERNAL_CLOCK_FREQUENCY / quotient; //this is the REAL
686 frequency being used
687  }
688  else //base freq: 66.667MHz
689  {
690  realClockFrequency = INTERNAL_CLOCK_FREQUENCY / quotient; //this is the REAL
691 frequency being used
692  }
693 
694  double factor = frequency / realClockFrequency;
695 
696  //The device needs the denominator and the denominator to be load into a 5 bit
697 register
698  //It will take two initial numerator and denominator bigger than necessary (to do not
699 loose precision)
700  //and divide them for their gcd. If they still do not fit in 5 bit, they are trunked
701 (divided by 2)
702  //untill they are less than 32
703  numerator = factor * 100; //we will work with 2 digits precision after the decimal
704 point denominator = 100;
705 
706  do
707  {
708  //We will need the GCD at some point in order to simplify fractions //taken from
709 other sources int gcd = numerator; int rest = denominator; int tmp;
710 
711  while (rest != 0)
712  {
713  tmp = rest;
714  rest = gcd % tmp;
715  gcd = tmp;
716  }
717  //Done finding the GCD
718 
719  if (gcd == 1) //if there's no GCD, just divide by 2 to find the nearest
720 approssimation with less bits
721  {
722  numerator /= 2;
723  denominator /= 2;
724  }
725  else
726  {
727  numerator /= gcd;
728  denominator /= gcd;
729  }
730 
731  }
732  while (denominator >= 32 || numerator >= 32);
733  std::cout << __COUT_HDR_FL__ << "Numerator: " << numerator << std::endl;
734  std::cout << __COUT_HDR_FL__ << "Denominator: " << denominator << std::endl;
735  setFrequencyRatio(buffer, numerator, denominator);
736  std::cout << __COUT_HDR_FL__ << "Done with clock frequency setup!!!" << std::endl;
737 }
738 //========================================================================================================================
739 bool FSSROtsFirmware::isClockStateExternal() //returns true if the clock state is External
740 {
741  if (BitManipulator::readBits(stripCSRRegisterValue_, 16, 1) == 1)
742  return true;
743  else
744  return false;
745 }
746 
747 //========================================================================================================================
748 void FSSROtsFirmware::setCSRRegister(uint32_t total)
749 {
750  stripCSRRegisterValue_ = total;
751 }
752 
753 //========================================================================================================================
754 void FSSROtsFirmware::writeCSRRegister(std::string& buffer)
755 {
756  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
757 }
758 
759 //========================================================================================================================
760 void FSSROtsFirmware::setPacketSizeStripCSR(uint32_t size)
761 {
762  if (size > 31)
763  std::cout << __COUT_HDR_FL__
764  << "ERROR: Maximum packet size is 31 while here you are trying to set "
765  << size << " packets!" << std::endl;
766  BitManipulator::insertBits(stripCSRRegisterValue_, size, 3, 5);
767  //write(buffer,STRIP_CSR, stripSCRRegisterValue_);
768 }
769 
770 //========================================================================================================================
771 void FSSROtsFirmware::enableChannelsStripCSR(bool channel0, bool channel1,
772  bool channel2, bool channel3, bool channel4, bool channel5)
773 {
774  BitManipulator::insertBits(stripCSRRegisterValue_, ((uint32_t) channel0)
775  + ((uint32_t) channel1 << 1) + ((uint32_t) channel2 << 2)
776  + ((uint32_t) channel3 << 3) + ((uint32_t) channel4 << 4)
777  + ((uint32_t) channel5 << 5), 8, 6);
778 }
779 
780 //========================================================================================================================
781 void FSSROtsFirmware::setExternalBCOClockSourceStripCSR(std::string clockSource)
782 {
783  if (clockSource == "External")
784  BitManipulator::insertBits(stripCSRRegisterValue_, 1, 16, 1);
785  else if (clockSource == "Internal")
786  BitManipulator::insertBits(stripCSRRegisterValue_, 0, 16, 1);
787 }
788 
789 //========================================================================================================================
790 void FSSROtsFirmware::setHaltStripCSR(bool set)
791 {
792  BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) set, 17, 1);
793 }
794 
795 //========================================================================================================================
796 void FSSROtsFirmware::enableBCOStripCSR(bool enable)
797 {
798  BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) enable, 19, 1);
799 }
800 
801 //========================================================================================================================
802 void FSSROtsFirmware::flushBuffersStripCSR(void)
803 {
804  BitManipulator::insertBits(stripCSRRegisterValue_, 1, 20, 1);
805 }
806 
807 //========================================================================================================================
808 void FSSROtsFirmware::resetTriggerCounterStripCSR(std::string& buffer)
809 {
810  BitManipulator::insertBits(stripCSRRegisterValue_, 1, 21, 1);
811  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
812 
813  BitManipulator::insertBits(stripCSRRegisterValue_, 0, 21, 1);
814  OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_);
815 }
816 
817 //========================================================================================================================
818 void FSSROtsFirmware::resetBCOCounterStripCSR(void)
819 {
820  BitManipulator::insertBits(stripCSRRegisterValue_, 1, 22, 1);
821 }
822 
823 //========================================================================================================================
824 void FSSROtsFirmware::enableTriggerStripCSR(bool enable)
825 {
826  BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) enable, 23, 1);
827 }
828 
829 //========================================================================================================================
830 void FSSROtsFirmware::sendTriggerDataStripCSR(bool send)
831 {
832  BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) send, 24, 1);
833 }
834 
835 //========================================================================================================================
836 void FSSROtsFirmware::sendTriggerNumberStripCSR(bool send)
837 {
838  BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) send, 25, 1);
839 }
840 
841 //========================================================================================================================
842 void FSSROtsFirmware::sendBCOStripCSR(bool send)
843 {
844  BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) send, 26, 1);
845 }
846 
847 //========================================================================================================================
848 void FSSROtsFirmware::enableStreamStripCSR(bool enable)
849 {
850  BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) enable, 27, 1);
851 }
852 
853 //========================================================================================================================
854 void FSSROtsFirmware::resetDCMStripCSR(bool clear)
855 {
856  BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) clear, 31, 1);
857 }
858 
859 //========================================================================================================================
860 uint32_t FSSROtsFirmware::waitDCMResetStripCSR(void)
861 {
862  uint32_t bitToCheck = 0;
863  BitManipulator::insertBits(bitToCheck, 1, 31, 2);
864  return bitToCheck;
865 }
866 
867 //========================================================================================================================
868 void FSSROtsFirmware::resetDAC(void)
869 {
870  BitManipulator::insertBits(stripResetRegisterValue_, 1, 27, 1);
871 }
872 
873 //========================================================================================================================
874 void FSSROtsFirmware::resetLink(bool channel0, bool channel1, bool channel2,
875  bool channel3, bool channel4, bool channel5)
876 {
877  stripResetRegisterValue_ = 0;
878  BitManipulator::insertBits(stripResetRegisterValue_,
879  ((uint32_t) channel0) + ((uint32_t) channel1 << 1)
880  + ((uint32_t) channel2 << 2) + ((uint32_t) channel3 << 3)
881  + ((uint32_t) channel4 << 4) + ((uint32_t) channel5 << 5),
882  0, 6);
883  BitManipulator::insertBits(stripResetRegisterValue_, 1, 29, 1);
884 
885  // write(buffer, STRIP_RESET, (1<<28) +
886  // ((uint32_t)channel0) +
887  // ((uint32_t)channel1<<1) +
888  // ((uint32_t)channel2<<2) +
889  // ((uint32_t)channel3<<3) +
890  // ((uint32_t)channel4<<4) +
891  // ((uint32_t)channel5<<5)
892  // );
893 
894 }
895 
896 //========================================================================================================================
897 void FSSROtsFirmware::clearErrors(bool channel0, bool channel1, bool channel2,
898  bool channel3, bool channel4, bool channel5)
899 {
900  stripResetRegisterValue_ = 0;
901  BitManipulator::insertBits(stripResetRegisterValue_,
902  ((uint32_t) channel0) + ((uint32_t) channel1 << 1)
903  + ((uint32_t) channel2 << 2) + ((uint32_t) channel3 << 3)
904  + ((uint32_t) channel4 << 4) + ((uint32_t) channel5 << 5),
905  0, 6);
906  BitManipulator::insertBits(stripResetRegisterValue_, 1, 29, 1);
907 }
908 
909 //========================================================================================================================
910 void FSSROtsFirmware::clearFIFO(bool channel0, bool channel1, bool channel2,
911  bool channel3, bool channel4, bool channel5)
912 {
913  stripResetRegisterValue_ = 0;
914  BitManipulator::insertBits(stripResetRegisterValue_,
915  ((uint32_t) channel0) + ((uint32_t) channel1 << 1)
916  + ((uint32_t) channel2 << 2) + ((uint32_t) channel3 << 3)
917  + ((uint32_t) channel4 << 4) + ((uint32_t) channel5 << 5),
918  0, 6);
919  BitManipulator::insertBits(stripResetRegisterValue_, 1, 30, 1);
920 }
921 
922 //========================================================================================================================
923 void FSSROtsFirmware::resetChip(bool channel0, bool channel1, bool channel2,
924  bool channel3, bool channel4, bool channel5)
925 {
926  stripResetRegisterValue_ = 0;
927  BitManipulator::insertBits(stripResetRegisterValue_,
928  ((uint32_t) channel0) + ((uint32_t) channel1 << 1)
929  + ((uint32_t) channel2 << 2) + ((uint32_t) channel3 << 3)
930  + ((uint32_t) channel4 << 4) + ((uint32_t) channel5 << 5),
931  0, 6);
932  BitManipulator::insertBits(stripResetRegisterValue_, 1, 31, 1);
933 }
934 
935 //========================================================================================================================
936 void FSSROtsFirmware::setFrequencyRatio(std::string& buffer, int numerator, int
937 denominator)
938 {
939  //The device need to load numerator minus one and denominator minus one, with an
940 internal address of 0x50 and 052 respectively OtsUDPFirmwareCore::write(buffer,
941 STRIP_BCO_DCM, 0x80500000 + (numerator - 1)); // Set BCOCLK numerator // was 0x80500003
942  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer,
943 STRIP_BCO_DCM, 0xf0000000); // Wait DCM write to finish // was 0x80000000
944 
945  OtsUDPFirmwareCore::write(buffer, STRIP_BCO_DCM, 0x80520000 + (denominator - 1)); //
946 Set BCOCLK denominator // was 0x80520001
947  //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer,
948 STRIP_BCO_DCM, 0xf0000000); // Wait DCM write to finish - BCO frequency should be 13.513
949 MHz // was 0x80000000
950 }
951 
952 //========================================================================================================================
953 void FSSROtsFirmware::BCOOffset(uint32_t offset)
954 {
955  BitManipulator::insertBits(stripTriggerCSRRegisterValue_, offset, 0, 4);
956 }
957 
958 //========================================================================================================================
959 void FSSROtsFirmware::selectSpyFIFO(uint32_t input)
960 {
961  BitManipulator::insertBits(stripTriggerCSRRegisterValue_, input, 4, 3);
962 }
963 
964 //========================================================================================================================
965 void FSSROtsFirmware::halt(bool halt)
966 {
967  BitManipulator::insertBits(stripTriggerCSRRegisterValue_, (uint32_t) halt, 7, 1);
968 }
969 
970 //========================================================================================================================
971 void FSSROtsFirmware::configureStripTriggerUnbiased(std::string& buffer)
972 {
973  OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_UNBIASED, 0x002805c); // Configure
974 unbiased trigger
975 }
976 
977 //========================================================================================================================
978 void FSSROtsFirmware::configureTriggerInputs(std::string& buffer)
979 {
980  OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_INPUT_0, 0x3f440000); // FSSR GOTHIT
981 trigger input channel 0,1 OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_INPUT_1,
982 0x3f440000); // FSSR GOTHIT trigger input channel 2,3 OtsUDPFirmwareCore::write(buffer,
983 STRIP_TRIG_INPUT_2, 0x0); // FSSR GOTHIT trigger input channel 4,5
984 }
985 
986 //========================================================================================================================
987 std::string FSSROtsFirmware::resetSlaveBCO(void)
988 {
989  std::string buffer;
990  OtsUDPFirmwareCore::write(buffer, (uint64_t)0xc5000000, (uint64_t)0x00000008);
991  return buffer;
992 }
993 
994  //========================================================================================================================
995  void FSSROtsFirmware::chipID(uint32_t size)
996  {
997  BitManipulator::insertBits(stripSCRegisterValue_, size, 0, 5);
998  }
999 
1000  //========================================================================================================================
1001  void FSSROtsFirmware::addressSlowControls(uint32_t size)
1002  {
1003  BitManipulator::insertBits(stripSCRegisterValue_, size, 5, 5);
1004  }
1005 
1006  //========================================================================================================================
1007  void FSSROtsFirmware::instructionSlowControls(uint32_t size)
1008  {
1009  BitManipulator::insertBits(stripSCRegisterValue_, size, 10, 3);
1010  }
1011 
1012  //========================================================================================================================
1013  void FSSROtsFirmware::channelreadSelect(uint32_t size)
1014  {
1015  BitManipulator::insertBits(stripSCRegisterValue_, size, 13, 3);
1016  }
1017 
1018  //========================================================================================================================
1019  void FSSROtsFirmware::channelMask(uint32_t size)
1020  {
1021  BitManipulator::insertBits(stripSCRegisterValue_, size, 16, 8);
1022  }
1023 
1024  //========================================================================================================================
1025  void FSSROtsFirmware::bitsLength(uint32_t length)
1026  {
1027  BitManipulator::insertBits(stripSCRegisterValue_, length, 26, 3);
1028  }
1029 
1030 
1031  //========================================================================================================================
1032  void FSSROtsFirmware::syncFallingBCO(bool sync)
1033  {
1034  BitManipulator::insertBits(stripSCRegisterValue_, (uint32_t)sync, 28, 1);
1035  }
1036 
1037  //========================================================================================================================
1038  void FSSROtsFirmware::syncRisingBCO(bool sync)
1039  {
1040  BitManipulator::insertBits(stripSCRegisterValue_, (uint32_t)sync, 29, 1);
1041  }
1042 
1043  //========================================================================================================================
1044  void FSSROtsFirmware::setRaw(bool set)
1045  {
1046  BitManipulator::insertBits(stripSCRegisterValue_, (uint32_t)set, 30, 1);
1047  }
1048 
1049  //========================================================================================================================
1050  void FSSROtsFirmware::initSlowControls(bool init)
1051  {
1052  BitManipulator::insertBits(stripSCRegisterValue_, (uint32_t)init, 31, 1);
1053  }
1054 
1055  //========================================================================================================================
1056  void FSSROtsFirmware::resetCount(bool reset)
1057  {
1058  BitManipulator::insertBits(stripAnalysisCSRRegisterValue_, (uint32_t)reset, 30, 1);
1059  }
1060 
1061  //========================================================================================================================
1062  void FSSROtsFirmware::setBCO_0(uint32_t void FSSROtsFirmware::BCOOffset(uint32_t offset)
1063  {
1064  BitManipulator::insertBits(stripTrigCSRRegisterValue_, offset, 0, 4);
1065  }input)
1066  {
1067  BitManipulator::insertBits(trigInputRegisterValue_, input, 0, 8);
1068  }
1069 
1070  //========================================================================================================================
1071  void FSSROtsFirmware::setBCO_1(uint32_t input)
1072  {
1073  BitManipulator::insertBits(trigInputRegisterValue_, input, 8, 8);
1074  }
1075 
1076  //========================================================================================================================
1077  void FSSROtsFirmware::trimFracBCO_0(uint32_t input)
1078  {
1079  BitManipulator::insertBits(trigInputRegisterValue_, input, 16, 4);
1080  }
1081 
1082  //========================================================================================================================
1083  void FSSROtsFirmware::trimFracBCO_1(uint32_t input)
1084  {
1085  BitManipulator::insertBits(trigInputRegisterValue_, input, 20, 4);
1086  }
1087 
1088  //========================================================================================================================
1089  void FSSROtsFirmware::enable_0(bool enable)
1090  {
1091  BitManipulator::insertBits(trigInputRegisterValue_, (uint32_t)enable, 28, 1);
1092  }
1093 
1094  //========================================================================================================================
1095  void FSSROtsFirmware::enable_1(bool enable)
1096  {
1097  BitManipulator::insertBits(trigInputRegisterValue_, (uint32_t)enable, 29, 1);
1098  }
1099 
1100  */