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00001 #include "otsdaq-components/DAQHardware/FSSROtsFirmware.h" 00002 00003 //#include "otsdaq-components/DAQHardware/FSSRFirmwareDefinitions.h" 00004 //#include "otsdaq-core/BitManipulator/BitManipulator.h" 00005 //#include "otsdaq-components/DetectorHardware/FSSRROCDefinitions.h" 00006 00007 #include "otsdaq-components/DAQHardware/FrontEndFirmwareBase.h" 00008 #include "otsdaq-components/DAQHardware/OtsUDPFirmwareCore.h" 00009 #include "otsdaq-components/DAQHardware/PurdueFirmwareCore.h" 00010 00011 #include <arpa/inet.h> 00012 #include <netinet/in.h> 00013 #include <sys/socket.h> 00014 #include "otsdaq-core/Macros/CoutMacros.h" 00015 #include "otsdaq-core/MessageFacility/MessageFacility.h" 00016 00017 #include <cstdlib> 00018 #include <iostream> 00019 00020 using namespace ots; 00021 00022 //======================================================================================================================== 00023 FSSROtsFirmware::FSSROtsFirmware(std::string communicationFirmwareType, 00024 unsigned int communicationFirmwareVersion, 00025 unsigned int applicationFirmwareVersion) 00026 : FSSRFirmwareBase(communicationFirmwareType, 00027 communicationFirmwareVersion, 00028 applicationFirmwareVersion) 00029 { 00030 } 00031 // //choose: OtsUDPFirmwareCore or PurdueFirmwareCore 00032 // if(communicationFirmwareType == FrontEndFirmwareBase::PURDUE_CORE_FIRMWARE_NAME) 00033 // communicationFirmwareInstance_ = new 00034 // PurdueFirmwareCore(communicationFirmwareVersion); if(communicationFirmwareType == 00035 // FrontEndFirmwareBase::OTS_CORE_FIRMWARE_NAME) communicationFirmwareInstance_ = 00036 // new OtsUDPFirmwareCore(communicationFirmwareVersion); else 00037 // { 00038 // __SS__ << "Unknown firmware type choice: " << choice << std::endl; 00039 // __COUT_ERR__ << ss.str(); 00040 // __SS_THROW__; 00041 // } 00042 // 00043 // 00044 // //make protocol a class member 00045 // //protocolInstance_ = new OtsFirmwareCore(version);//AUG-17-2017 RAR dissociated 00046 // because function calls are entirely independent from PURDUE firmware calls // 00048 // //assert(protocolInstance_ != NULL); 00049 // //returns either new OtsUDPFirmware or new PurdueFirmwareCore, 00050 // //now we can call write/read etc with protocol->write, protocol->read, etc 00051 //} 00052 00053 //======================================================================================================================== 00054 FSSROtsFirmware::~FSSROtsFirmware(void) 00055 { 00056 // delete protocolInstance_; 00057 // protocolInstance_ = NULL; 00058 } 00059 00060 //======================================================================================================================== 00061 void FSSROtsFirmware::init(void) {} 00062 00063 /* 00064 //======================================================================================================================== 00065 std::string FSSROtsFirmware::configureClocks(std::string source, double frequency) 00066 { 00067 std::cout << __COUT_HDR_FL__ << "Writing Clock configuration!" << std::endl; 00068 00069 std::string buffer; 00070 //NoNeedNowwrite(buffer, ETHIO_DESTINATION_PORT, 0x0000b798); // Listen port for 00071 ethio stuff 00072 00073 setPacketSizeStripCSR(6); 00074 setExternalBCOClockSourceStripCSR(source); //(source) 00075 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); // Reset CSR - 00076 reset trigger counter, external 27 MHz clock 00077 00078 resetDCMStripCSR(true); 00079 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); // Set reset to 00080 DCM 00081 00082 resetDCMStripCSR(false); 00083 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); // Clear reset 00084 to DCM 00085 00086 ; 00087 //FIXME? Does Nothing RAR Aug 2017// OtsUDPFirmwareCore::waitClear(buffer, STRIP_CSR, 00088 waitDCMResetStripCSR()); // Wait for DCM to lock 00089 00090 OtsUDPFirmwareCore::write(buffer, STRIP_TRIM_CSR, 0x00002000); // MCLKB edge for 00091 channel 5 // was 0x00002000 00092 00093 setFrequencyFromClockState(buffer, frequency); 00094 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00095 00096 resetDCMStripCSR(true); 00097 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00098 00099 resetDCMStripCSR(false); 00100 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00101 00102 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer, STRIP_CSR, 00103 waitDCMResetStripCSR()); // Wait for DCM to lock std::cout << __COUT_HDR_FL__ << 00104 "stripCSRRegisterValue :" << std::hex << stripCSRRegisterValue_ << std::dec << std::endl; 00105 00106 return buffer; 00107 } 00108 00109 //======================================================================================================================== 00110 std::string FSSROtsFirmware::resetDetector(int channel) 00111 { 00112 std::cout << __COUT_HDR_FL__ << "Resetting detector!" << std::endl; 00113 std::string buffer; 00114 if (channel == -1)//reset all channels 00115 { 00116 //write(buffer,STRIP_RESET,0xd000003f); // Issue reset 00117 OtsUDPFirmwareCore::write(buffer, STRIP_RESET, 0xf000003f); // Issue reset // was 00118 0xf000003f 00119 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer, 00120 STRIP_RESET, 0xf0000000); // Wait for reset to complete // was 0xf0000000 } else 00121 { 00122 OtsUDPFirmwareCore::write(buffer, STRIP_RESET, 0xf000003f); // Issue reset 00123 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer, 00124 STRIP_RESET, 0xf0000000); // Wait for reset to complete 00125 } 00126 00127 return buffer; 00128 } 00129 00130 //======================================================================================================================== 00131 std::string FSSROtsFirmware::enableTrigger(void) 00132 { 00133 std::string buffer; 00134 std::cout << __COUT_HDR_FL__ << "Enabling Trigger!!!" << std::endl; 00135 std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue in :" << std::hex << 00136 stripCSRRegisterValue_ << std::dec << std::endl; 00137 00138 setHaltStripCSR(1);//WARNING THIS IS CLEARED BY THE MASTER BUT IF THERE IS NO MASTER 00139 NOTHING WORKS UNLESS THE BIT IS UNSET 00140 //setHaltStripCSR(0);//WARNING THIS IS CLEARED BY THE MASTER BUT IF THERE IS NO MASTER 00141 NOTHING WORKS UNLESS THE BIT IS UNSET sendTriggerDataStripCSR(true); 00142 sendTriggerNumberStripCSR(true); 00143 sendBCOStripCSR(true); 00144 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00145 00146 stripTriggerCSRRegisterValue_ = 0; 00147 BCOOffset(4); 00148 OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_CSR, stripTriggerCSRRegisterValue_); // 00149 BCO offset // was 0x00000004 00150 00151 // write(buffer,STRIP_TRIG_INPUT_0,0x1f060040); // FSSR GOTHIT trigger input - 00152 timed in for the 27 MHz external clock 00153 // write(buffer,STRIP_TRIG_INPUT_3,0x3f874040); // Unbiased trigger input + 00154 external trigger 00155 00156 configureStripTriggerUnbiased(buffer); 00157 00158 configureTriggerInputs(buffer); 00159 00160 //FIXME for IP .36 the number to set is 0x20401000 00161 00162 if (OtsUDPFirmwareCore::version_ == 1) 00163 OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_INPUT_3, 0x20401000); // Turn on 00164 streaming hits along with BCO data else if (OtsUDPFirmwareCore::version_ == 2) 00165 OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_INPUT_3, 0x20301000); // Turn on 00166 streaming hits along with BCO data else 00167 { 00168 __SS__ << "what version is this?" << 00169 OtsUDPFirmwareCore::version_ << std::endl; 00170 __COUT_ERR__ << "\n" << ss.str(); 00171 __SS_THROW__; 00172 } 00173 std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue out:" << std::hex << 00174 stripCSRRegisterValue_ << std::dec << std::endl; std::cout << __COUT_HDR_FL__ << "Done 00175 enabling Trigger!!!" << std::endl; 00176 00177 return buffer; 00178 } 00179 00180 //======================================================================================================================== 00181 void FSSROtsFirmware::readBurstDestinationIP(std::string& buffer) 00182 { 00183 OtsUDPFirmwareCore::read(buffer, (uint64_t)0x0000000100000006); 00184 } 00185 00186 //======================================================================================================================== 00187 void FSSROtsFirmware::readBurstDestinationMAC(std::string& buffer) 00188 { 00189 OtsUDPFirmwareCore::read(buffer, (uint64_t)0x0000000100000007); 00190 } 00191 00192 //======================================================================================================================== 00193 void FSSROtsFirmware::readBurstDestinationPort(std::string& buffer) 00194 { 00195 OtsUDPFirmwareCore::read(buffer, (uint64_t)0x0000000100000008); 00196 } 00197 00198 //======================================================================================================================== 00199 void FSSROtsFirmware::writeBurstDestinationIP(std::string& buffer, const uint64_t value) 00200 { 00201 OtsUDPFirmwareCore::write(buffer, (uint64_t)0x0000000100000006, value); 00202 } 00203 00204 //======================================================================================================================== 00205 void FSSROtsFirmware::writeBurstDestinationMAC(std::string& buffer, const uint64_t value) 00206 { 00207 OtsUDPFirmwareCore::write(buffer, (uint64_t)0x0000000100000007, value); 00208 } 00209 00210 //======================================================================================================================== 00211 void FSSROtsFirmware::writeBurstDestinationPort(std::string& buffer, const uint64_t value) 00212 { 00213 OtsUDPFirmwareCore::write(buffer, 0x0000000100000008, value); 00214 } 00215 00216 //======================================================================================================================== 00217 std::string FSSROtsFirmware::resetBCO(void) 00218 { 00219 std::cout << __COUT_HDR_FL__ << "Reset BCO!!!" << std::endl; 00220 std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue in :" << std::hex << 00221 stripCSRRegisterValue_ << std::dec << std::endl; std::string buffer; 00222 00223 resetTriggerCounterStripCSR(buffer); 00224 //write(buffer, STRIP_CSR, stripCSRRegisterValue_);//the write is done in the reset 00225 std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue :" << std::hex << 00226 stripCSRRegisterValue_ << std::dec << std::endl; 00227 00228 //msg->Write(STRIP_SC_CSR,0x90000b95|(chmask<<16)); 00229 //write(buffer,STRIP_SC_CSR,0x900f0b95);// This is the <SCR,set> command with the bit 00230 set to sync SHIFT with BCO=0. 00231 00232 00233 enableBCOStripCSR(true); 00234 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00235 std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue out:" << std::hex << 00236 stripCSRRegisterValue_ << std::dec << std::endl; std::cout << __COUT_HDR_FL__ << "Done 00237 reset BCO!!!" << std::endl; 00238 00239 return buffer; 00240 } 00241 00242 //======================================================================================================================== 00243 std::string FSSROtsFirmware::startStream(bool channel0, bool channel1, bool channel2, bool 00244 channel3, bool channel4, bool channel5) 00245 { 00246 std::cout << __COUT_HDR_FL__ << "Start Stream!" << std::endl; 00247 std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue in:" << std::hex << 00248 stripCSRRegisterValue_ << std::dec << std::endl; std::string buffer; 00249 00250 std::cout << __COUT_HDR_FL__ << " channel0 " << channel0 << " channel1 " << channel1 00251 << " channel2 " << channel2 << " channel3 " << channel3 << " channel4 " << channel4 << " 00252 channel5 " << channel5 << std::endl; 00253 00254 enableChannelsStripCSR(channel0, channel1, channel2, channel3, channel4, channel5); 00255 // if (version_ == 1) 00256 // enableChannelsStripCSR(true, true, true, true, false, false); 00257 // else if (version_ == 2) 00258 // enableChannelsStripCSR(true, true, true, true, true, true); 00259 00260 enableStreamStripCSR(true); // Turn on streaming hits along with BCO data // was 00261 0x0f000f30 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00262 00263 std::cout << __COUT_HDR_FL__ << "stripCSRRegisterValue out:" << std::hex << 00264 stripCSRRegisterValue_ << std::dec << std::endl; std::cout << __COUT_HDR_FL__ << "Done 00265 start Stream!" << std::endl; 00266 00267 return buffer; 00268 } 00269 00270 //======================================================================================================================== 00271 std::string FSSROtsFirmware::stopStream(void) 00272 { 00273 std::string buffer; 00274 enableChannelsStripCSR(false, false, false, false, false, false); 00275 enableStreamStripCSR(false); 00276 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00277 return buffer; 00278 } 00279 00280 //======================================================================================================================== 00281 void FSSROtsFirmware::makeDACSequence(FirmwareSequence<uint64_t>& sequence, 00282 unsigned int channel, const ROCStream& rocStream) 00283 { 00284 const ROCDACs& rocDACs = rocStream.getROCDACs(); 00285 for (DACList::const_iterator it = rocDACs.getDACList().begin(); it 00286 != rocDACs.getDACList().end(); it++) 00287 { 00288 //if(it->first != "SendData" && it->first != "RejectHits") continue; 00289 uint64_t data = FSSRROCDefinitions::makeDACWriteCommand( 00290 rocStream.getFEWROCAddress(), it->first, it->second.second); 00291 sequence.pushBack(ChannelFIFOAddress[channel], data); 00292 sequence.pushBack(ChannelFIFOAddress[channel], 00293 BitManipulator::insertBits(data, (uint64_t) 0x48, 56, 8)); 00294 //set WRITE 00295 sequence.pushBack(ChannelFIFOAddress[channel], 00296 BitManipulator::insertBits(data, (uint64_t) 1, 60, 1)); 00297 //clr WRITE 00298 sequence.pushBack(ChannelFIFOAddress[channel], 00299 BitManipulator::insertBits(data, (uint64_t) 0, 60, 1)); 00300 //clr TALK 00301 sequence.pushBack(ChannelFIFOAddress[channel], 00302 BitManipulator::insertBits(data, (uint64_t) 0, 62, 1)); 00303 sequence.pushBack(ChannelFIFOAddress[channel], 00304 BitManipulator::insertBits(data, (uint64_t) 0x40, 56, 8)); 00305 //break; 00306 } 00307 } 00308 00309 //======================================================================================================================== 00310 void FSSROtsFirmware::makeDACSequence(FirmwareSequence<uint32_t>& sequence, 00311 unsigned int channel, const ROCStream& rocStream) 00312 { 00313 const ROCDACs& rocDACs = rocStream.getROCDACs(); 00314 for (DACList::const_iterator it = rocDACs.getDACList().begin(); it 00315 != rocDACs.getDACList().end(); it++) 00316 { 00317 //RYAN 00318 //if(it->first != "SendData" && it->first != "RejectHits") continue; 00319 uint64_t data = 00320 FSSRROCDefinitions::makeDACWriteCommand(rocStream.getFEWROCAddress(), it->first, 00321 it->second.second); 00322 //sequence.pushBack(ChannelFIFOAddress[channel], data); 00323 //sequence.pushBack(ChannelFIFOAddress[channel], 00324 BitManipulator::insertBits(data,(uint32_t)0x48,56,8)); 00325 //set WRITE 00326 //sequence.pushBack(ChannelFIFOAddress[channel], 00327 BitManipulator::insertBits(data,(uint32_t)1,60,1)); 00328 //clr WRITE 00329 //sequence.pushBack(ChannelFIFOAddress[channel], 00330 BitManipulator::insertBits(data,(uint32_t)0,60,1)); 00331 //clr TALK 00332 //sequence.pushBack(ChannelFIFOAddress[channel], 00333 BitManipulator::insertBits(data,(uint32_t)0,62,1)); 00334 //sequence.pushBack(ChannelFIFOAddress[channel], 00335 BitManipulator::insertBits(data,(uint32_t)0x40,56,8)); 00336 00337 00338 //if(it->first != "SendData" && it->first != "RejectHits") continue; 00339 uint32_t data = FSSRROCDefinitions::makeDACWriteHeader( 00340 rocStream.getFEWROCAddress(), it->first); 00341 //Insert channel 00342 BitManipulator::insertBits(data, 1, 16 + channel, 1); 00343 sequence.pushBack(ChannelFIFOAddress[channel], it->second.second); 00344 std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " << it->first 00345 << " value: " 00346 << it->second.second << std::hex << " -> Data: " << data << std::dec 00347 << std::endl; 00348 sequence.pushBack(STRIP_SC_CSR, data); 00349 } 00350 } 00351 00352 //======================================================================================================================== 00353 void FSSROtsFirmware::makeDACBuffer(std::string& buffer, 00354 unsigned int channel, const ROCStream& rocStream) 00355 { 00356 std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Channel: " << channel << 00357 std::endl; const ROCDACs& rocDACs = rocStream.getROCDACs(); for (DACList::const_iterator 00358 it = rocDACs.getDACList().begin(); it != rocDACs.getDACList().end(); it++) 00359 { 00360 std::string bufferElement; 00361 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(bufferElement, 00362 STRIP_SC_CSR, 0x80000000); uint32_t registerHeader = 0; 00363 //FIXME This must go in the FSSRROCDefinitions stuff 00364 if (it->first != "RejectHits" && it->first != "SendData") 00365 { 00366 OtsUDPFirmwareCore::write(bufferElement, ChannelFIFOAddress[channel], 00367 it->second.second); registerHeader = FSSRROCDefinitions::makeDACWriteHeader( 00368 rocStream.getFEWROCAddress(), it->first); 00369 //std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " << 00370 it->first << " value: " << it->second.second << std::hex << " -> Data: " << registerHeader 00371 << std::dec << std::endl; 00372 //Insert channel 00373 BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1); 00374 } 00375 else 00376 { 00377 if (it->second.second == 1 || it->second.second == 2) 00378 { 00379 registerHeader = FSSRROCDefinitions::makeDACSetHeader( 00380 rocStream.getFEWROCAddress(), it->first); 00381 //Insert channel 00382 BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1); 00383 } 00384 else if (it->second.second == 0 || it->second.second == 5) 00385 { 00386 registerHeader = FSSRROCDefinitions::makeDACResetHeader( 00387 rocStream.getFEWROCAddress(), it->first); 00388 //Insert channel 00389 BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1); 00390 } 00391 else 00392 std::cout << __COUT_HDR_FL__ << "Register value for : " << it->first 00393 << " doesn't have a value I expect -> value = " 00394 << it->second.second << std::endl; 00395 00396 } 00397 //std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " << it->first 00398 << " value: " << it->second.second << std::hex << " -> Data: " << registerHeader << 00399 std::dec << std::endl; OtsUDPFirmwareCore::write(bufferElement, STRIP_SC_CSR, 00400 registerHeader); 00401 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(bufferElement, 00402 STRIP_SC_CSR, 0x80000000); 00403 00404 //buffer.push_back(bufferElement); 00405 buffer += bufferElement; 00406 //break; 00407 } 00408 } 00409 00410 //======================================================================================================================== 00411 void FSSROtsFirmware:: makeDACBuffer(std::vector<std::string>& buffer, unsigned int 00412 channel, const ROCStream& rocStream) 00413 { 00414 00415 std::cout << __COUT_HDR_FL__ << "\tMaking DAC Buffer" << std::endl; 00416 00417 int limitCount = 0; 00418 unsigned int singleVectorCount = 0; 00419 00420 std::string alternateBuffer; 00421 00422 std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Channel: " << channel << 00423 std::endl; const ROCDACs& rocDACs = rocStream.getROCDACs(); 00424 //std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Number of DACs: " << 00425 rocDACs.getDACList().size() << std::endl; std::string bufferElement; for 00426 (DACList::const_iterator it = rocDACs.getDACList().begin(); it != 00427 rocDACs.getDACList().end(); it++) 00428 { 00429 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(bufferElement, 00430 STRIP_SC_CSR, 0x80000000); uint32_t registerHeader = 0; 00431 //FIXME This must go in the FSSRROCDefinitions stuff 00432 if (it->first != "RejectHits" && it->first != "SendData") 00433 { 00434 OtsUDPFirmwareCore::write(bufferElement, ChannelFIFOAddress[channel], 00435 it->second.second); registerHeader = FSSRROCDefinitions::makeDACWriteHeader( 00436 rocStream.getFEWROCAddress(), it->first); 00437 std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " << 00438 it->first << " value: " << it->second.second << std::hex << " -> Data: " << registerHeader 00439 << std::dec << std::endl; 00440 //Insert channel 00441 BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1); 00442 } 00443 else 00444 { 00445 if (it->second.second == 1 || it->second.second == 2) 00446 { 00447 registerHeader = FSSRROCDefinitions::makeDACSetHeader( 00448 rocStream.getFEWROCAddress(), it->first); 00449 //Insert channel 00450 BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1); 00451 } 00452 else if (it->second.second == 0 || it->second.second == 5) 00453 { 00454 registerHeader = FSSRROCDefinitions::makeDACResetHeader( 00455 rocStream.getFEWROCAddress(), it->first); 00456 //Insert channel 00457 BitManipulator::insertBits(registerHeader, 1, 16 + channel, 1); 00458 } 00459 else 00460 std::cout << __COUT_HDR_FL__ << "Register value for : " << it->first 00461 << " doesn't have a value I expect -> value = " 00462 << it->second.second << std::endl; 00463 00464 } 00465 //std::cout << __COUT_HDR_FL__ << __PRETTY_FUNCTION__ << "Register: " << it->first 00466 << " value: " << it->second.second << std::hex << " -> Data: " << registerHeader << 00467 std::dec << std::endl; OtsUDPFirmwareCore::write(bufferElement, STRIP_SC_CSR, 00468 registerHeader); 00469 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(bufferElement, 00470 STRIP_SC_CSR, 0x80000000); 00471 00472 //alternateBuffer += bufferElement; 00473 limitCount++; 00474 singleVectorCount++; 00475 00476 if (limitCount == STIB_DAC_WRITE_MAX) 00477 { 00478 std::cout << __COUT_HDR_FL__ << "\tBuffer lenght:" << bufferElement.size() << 00479 std::endl; buffer.push_back(bufferElement); limitCount = 0; bufferElement.clear(); 00480 } 00481 else if (singleVectorCount == rocDACs.getDACList().size()) //case for imcomplete 00482 packet 00483 { 00484 buffer.push_back(bufferElement); 00485 } 00486 00487 //buffer.push_back(bufferElement); 00488 //break; 00489 } 00490 std::cout << __COUT_HDR_FL__ << "\tDone making DAC Buffer" << std::endl; 00491 00492 } 00493 00494 //======================================================================================================================== 00495 void FSSROtsFirmware::makeMaskBuffer(std::string& buffer, unsigned int channel, 00496 const ROCStream& rocStream) 00497 { 00498 std::cout << __COUT_HDR_FL__ << "Making mask! " << std::endl; 00499 makeMaskBuffer(buffer, channel, rocStream, "Kill"); 00500 // makeMaskSequence(buffer, channel, rocStream, "Inject"); 00501 } 00502 00503 //======================================================================================================================== 00504 void FSSROtsFirmware::makeMaskBuffer(std::string& buffer, unsigned int channel, const 00505 ROCStream& rocStream, const std::string& registerName) 00506 { 00507 std::cout << __COUT_HDR_FL__ << "\tMaking mask! " << std::endl; 00508 int chipId = rocStream.getFEWROCAddress(); 00509 std::string mask = rocStream.getROCMask(); 00510 std::cout << __COUT_HDR_FL__ << "\tMask length: " << mask.length() << std::endl; 00511 00512 unsigned int data[4] = { 0, 0, 0, 0 }; 00513 00514 char val; 00515 //int j = 0; 00516 for (unsigned int d = 0; d < 4; d++) 00517 { //d goes from 0 to 4. 4 bytes 00518 //std::cout << __COUT_HDR_FL__ << "---------------------" << d << 00519 "-------------------" << std::endl; for (unsigned int m = 0; m < 8 * 4; m++) { //m goes 00520 from 0 to 31, since each byte has 8 bits, there are 32 bits val = mask[(8 * 4 * d) + m]; 00521 //assigns to val the value of the corresponding bit. 0-31, 32-63, 64-95, 96-127. it goes 00522 through each of the 128 bits 00523 //std::cout << __COUT_HDR_FL__ << "---------------------" << j++ << std::endl; 00524 //std::cout << __COUT_HDR_FL__ << "data[" << d << "] before: " << std::hex << 00525 data[d] << std::dec << std::endl; data[d] |= (unsigned int) atoi(&val) << (8 * 4 - 1 - m); 00526 //std::cout << __COUT_HDR_FL__ << "(unsigned int) atoi(&val): " << (unsigned 00527 int) atoi(&val) << std::endl; 00528 //std::cout << __COUT_HDR_FL__ << "data[" << d << "] after: " << std::hex << 00529 data[d] << std::dec << std::endl; 00530 //std::cout << __COUT_HDR_FL__ << std::hex << "D: " << data[d] << " Val: " << 00531 (unsigned int)atoi(&val) << " index: " << std::dec << (8*4-1-m) << " bit: " << 00532 mask[(8*4*d)+m] << std::dec << std::endl; 00533 } 00534 // 00535 } 00536 00537 int i, ierr; 00538 unsigned int w; 00539 unsigned char len = 4; 00540 unsigned char addr = 17;//Kill 00541 unsigned char bitMask = 1 << channel; 00542 unsigned char inst = WRITE; 00543 00544 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer, 00545 STRIP_SC_CSR, 0x80000000); 00546 00547 for (i = 0; i < 4; i++) 00548 //write(buffer, STRIP_SCI + 4 * i, data[i]); 00549 OtsUDPFirmwareCore::write(buffer, STRIP_SCI + 4 * (4 - i - 1), data[i]); 00550 00551 w = 0x80000000 | (len << 24) | (bitMask << 16) | (inst << 10) | (addr << 5) | chipId; 00552 00553 //ierr = OtsUDPFirmwareCore::write(buffer, STRIP_SC_CSR, w); 00554 OtsUDPFirmwareCore::write(buffer, STRIP_SC_CSR, w); 00555 00556 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer, 00557 STRIP_SC_CSR, 0x80000000); 00558 } 00559 00560 //======================================================================================================================== 00561 void FSSROtsFirmware::makeMaskSequence(FirmwareSequence<uint64_t>& sequence, 00562 unsigned int channel, const ROCStream& rocStream) 00563 { 00564 std::cout << __COUT_HDR_FL__ << "Making mask! " << std::endl; 00565 makeMaskSequence(sequence, channel, rocStream, "Kill"); 00566 // makeMaskSequence(sequence, channel, rocStream, "Inject"); 00567 } 00568 00569 //======================================================================================================================== 00570 void FSSROtsFirmware::makeMaskSequence(FirmwareSequence<uint32_t>& sequence, 00571 unsigned int channel, const ROCStream& rocStream) 00572 { 00573 std::cout << __COUT_HDR_FL__ << "Making mask! " << std::endl; 00574 makeMaskSequence(sequence, channel, rocStream, "Kill"); 00575 // makeMaskSequence(channel,rocStream,sequence,"Inject"); 00576 } 00577 00578 //======================================================================================================================== 00579 void FSSROtsFirmware::makeMaskSequence(FirmwareSequence<uint64_t>& sequence, 00580 unsigned int channel, const ROCStream& rocStream, 00581 const std::string& registerName) 00582 { 00583 int chipId = rocStream.getFEWROCAddress();//9, 14 or 21 bcast 00584 std::string mask = rocStream.getROCMask(); 00585 std::cout << __COUT_HDR_FL__ << "Mask length: " << mask.length() << std::endl; 00586 00587 uint64_t uInt64Data = 0; 00588 std::string stringData = ""; 00589 00590 //have to manually set every bit for mask writes. 00591 //reset fifo 00592 //download every bit (shift_in and shift_ctrl) to fifo (setup muxes and control lines) 00593 //configure muxes for readout 00594 //commence readout 00595 00596 //FIFO Controls - byte 5 (7:0) 00597 //7 - FIFO Clock 00598 //6 - Shift Ctrl bit 00599 //MASK_CELL_H - Shift In bit 00600 //MUX Controls - byte 0 (7:0) 00601 //7 - Read En/Output MUX sel (1 for masks) 00602 //1 - Write En for mux 00603 //0 - Reset Fifo 00604 00605 //reset fifo 00606 BitManipulator::insertBits(uInt64Data, 0x1, 56, 8); 00607 sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00608 00609 //configure fifo for write 00610 BitManipulator::insertBits(uInt64Data, 0x2, 56, 8); 00611 sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00612 00613 //Download every bit (shift_in and shift_control) to fifo (setup muxes and control 00614 lines) 00615 //Bit 7 of data is FIFO clock, bit 6 is shift_control, bit 5 is shift_in 00616 //start bits (ctrl 0, data 0 => ctrl 1, data 0) 00617 00618 BitManipulator::insertBits(uInt64Data, 0x40, 16, 8);//(0<<7) | (1<<6) | (0<<5) 00619 sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00620 BitManipulator::insertBits(uInt64Data, 0xc0, 16, 8);//(1<<7) | (1<<6) | (0<<5) -> 00621 clock the data in the fifo sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00622 00623 stringData = FSSRROCDefinitions::makeMaskWriteCommand(chipId, 00624 registerName, mask); 00625 00626 uint8_t data; 00627 for (unsigned int s = 0; s < stringData.length(); s++) 00628 for (int b = 8 - 1; b >= 0 && (s * 8 + 8 - b < 13 + 128); b--) 00629 { 00630 //std::cout << __COUT_HDR_FL__ << "S: " << s << " val: " << 00631 stringData.data()[s] << " b: " << b << " bit: " << ((stringData.data()[s]>>b)&1) << 00632 std::endl; data = 0x40 | (((stringData.data()[s] >> b) & 1) << 5); 00633 BitManipulator::insertBits(uInt64Data, (uint64_t) data, 16, 8); 00634 sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00635 data |= 0x80; 00636 BitManipulator::insertBits(uInt64Data, (uint64_t) data, 16, 8); 00637 sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00638 } 00639 00640 //reset Shift Control 00641 BitManipulator::insertBits(uInt64Data, 0x0, 16, 8); 00642 sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00643 BitManipulator::insertBits(uInt64Data, 0x80, 16, 8); 00644 sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00645 00646 //configure muxes for readout 00647 BitManipulator::insertBits(uInt64Data, 0x0, 56, 8); 00648 sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00649 00650 //commence readout 00651 BitManipulator::insertBits(uInt64Data, 0x80, 56, 8); 00652 sequence.pushBack(ChannelFIFOAddress[channel], uInt64Data); 00653 00654 } 00655 00656 //======================================================================================================================== 00657 void FSSROtsFirmware::makeMaskSequence(FirmwareSequence<uint32_t>& sequence, 00658 unsigned int channel, const ROCStream& rocStream, 00659 const std::string& registerName) 00660 {} 00661 00662 //======================================================================================================================== 00663 std::string FSSROtsFirmware::readCSRRegister() 00664 { 00665 std::string buffer; 00666 OtsUDPFirmwareCore::read(buffer,STRIP_CSR); 00667 return buffer; 00668 } 00669 00670 //======================================================================================================================== 00671 void FSSROtsFirmware::setFrequencyFromClockState(std::string& buffer, double frequency) 00672 { 00673 std::cout << __COUT_HDR_FL__ << "Setting up clock frequency!!!" << std::endl; 00674 00675 int quotient; 00676 int numerator; 00677 int denominator; 00678 double realClockFrequency; 00679 00680 if (BitManipulator::readBits(stripCSRRegisterValue_, 17, 1) == 1) //if fastBCO is 00681 enabled quotient = 4; else //normal cases quotient = 8; 00682 00683 if (isClockStateExternal()) //base freq: 54MHz 00684 { 00685 realClockFrequency = EXTERNAL_CLOCK_FREQUENCY / quotient; //this is the REAL 00686 frequency being used 00687 } 00688 else //base freq: 66.667MHz 00689 { 00690 realClockFrequency = INTERNAL_CLOCK_FREQUENCY / quotient; //this is the REAL 00691 frequency being used 00692 } 00693 00694 double factor = frequency / realClockFrequency; 00695 00696 //The device needs the denominator and the denominator to be load into a 5 bit 00697 register 00698 //It will take two initial numerator and denominator bigger than necessary (to do not 00699 loose precision) 00700 //and divide them for their gcd. If they still do not fit in 5 bit, they are trunked 00701 (divided by 2) 00702 //untill they are less than 32 00703 numerator = factor * 100; //we will work with 2 digits precision after the decimal 00704 point denominator = 100; 00705 00706 do 00707 { 00708 //We will need the GCD at some point in order to simplify fractions //taken from 00709 other sources int gcd = numerator; int rest = denominator; int tmp; 00710 00711 while (rest != 0) 00712 { 00713 tmp = rest; 00714 rest = gcd % tmp; 00715 gcd = tmp; 00716 } 00717 //Done finding the GCD 00718 00719 if (gcd == 1) //if there's no GCD, just divide by 2 to find the nearest 00720 approssimation with less bits 00721 { 00722 numerator /= 2; 00723 denominator /= 2; 00724 } 00725 else 00726 { 00727 numerator /= gcd; 00728 denominator /= gcd; 00729 } 00730 00731 } 00732 while (denominator >= 32 || numerator >= 32); 00733 std::cout << __COUT_HDR_FL__ << "Numerator: " << numerator << std::endl; 00734 std::cout << __COUT_HDR_FL__ << "Denominator: " << denominator << std::endl; 00735 setFrequencyRatio(buffer, numerator, denominator); 00736 std::cout << __COUT_HDR_FL__ << "Done with clock frequency setup!!!" << std::endl; 00737 } 00738 //======================================================================================================================== 00739 bool FSSROtsFirmware::isClockStateExternal() //returns true if the clock state is External 00740 { 00741 if (BitManipulator::readBits(stripCSRRegisterValue_, 16, 1) == 1) 00742 return true; 00743 else 00744 return false; 00745 } 00746 00747 //======================================================================================================================== 00748 void FSSROtsFirmware::setCSRRegister(uint32_t total) 00749 { 00750 stripCSRRegisterValue_ = total; 00751 } 00752 00753 //======================================================================================================================== 00754 void FSSROtsFirmware::writeCSRRegister(std::string& buffer) 00755 { 00756 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00757 } 00758 00759 //======================================================================================================================== 00760 void FSSROtsFirmware::setPacketSizeStripCSR(uint32_t size) 00761 { 00762 if (size > 31) 00763 std::cout << __COUT_HDR_FL__ 00764 << "ERROR: Maximum packet size is 31 while here you are trying to set " 00765 << size << " packets!" << std::endl; 00766 BitManipulator::insertBits(stripCSRRegisterValue_, size, 3, 5); 00767 //write(buffer,STRIP_CSR, stripSCRRegisterValue_); 00768 } 00769 00770 //======================================================================================================================== 00771 void FSSROtsFirmware::enableChannelsStripCSR(bool channel0, bool channel1, 00772 bool channel2, bool channel3, bool channel4, bool channel5) 00773 { 00774 BitManipulator::insertBits(stripCSRRegisterValue_, ((uint32_t) channel0) 00775 + ((uint32_t) channel1 << 1) + ((uint32_t) channel2 << 2) 00776 + ((uint32_t) channel3 << 3) + ((uint32_t) channel4 << 4) 00777 + ((uint32_t) channel5 << 5), 8, 6); 00778 } 00779 00780 //======================================================================================================================== 00781 void FSSROtsFirmware::setExternalBCOClockSourceStripCSR(std::string clockSource) 00782 { 00783 if (clockSource == "External") 00784 BitManipulator::insertBits(stripCSRRegisterValue_, 1, 16, 1); 00785 else if (clockSource == "Internal") 00786 BitManipulator::insertBits(stripCSRRegisterValue_, 0, 16, 1); 00787 } 00788 00789 //======================================================================================================================== 00790 void FSSROtsFirmware::setHaltStripCSR(bool set) 00791 { 00792 BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) set, 17, 1); 00793 } 00794 00795 //======================================================================================================================== 00796 void FSSROtsFirmware::enableBCOStripCSR(bool enable) 00797 { 00798 BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) enable, 19, 1); 00799 } 00800 00801 //======================================================================================================================== 00802 void FSSROtsFirmware::flushBuffersStripCSR(void) 00803 { 00804 BitManipulator::insertBits(stripCSRRegisterValue_, 1, 20, 1); 00805 } 00806 00807 //======================================================================================================================== 00808 void FSSROtsFirmware::resetTriggerCounterStripCSR(std::string& buffer) 00809 { 00810 BitManipulator::insertBits(stripCSRRegisterValue_, 1, 21, 1); 00811 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00812 00813 BitManipulator::insertBits(stripCSRRegisterValue_, 0, 21, 1); 00814 OtsUDPFirmwareCore::write(buffer, STRIP_CSR, stripCSRRegisterValue_); 00815 } 00816 00817 //======================================================================================================================== 00818 void FSSROtsFirmware::resetBCOCounterStripCSR(void) 00819 { 00820 BitManipulator::insertBits(stripCSRRegisterValue_, 1, 22, 1); 00821 } 00822 00823 //======================================================================================================================== 00824 void FSSROtsFirmware::enableTriggerStripCSR(bool enable) 00825 { 00826 BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) enable, 23, 1); 00827 } 00828 00829 //======================================================================================================================== 00830 void FSSROtsFirmware::sendTriggerDataStripCSR(bool send) 00831 { 00832 BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) send, 24, 1); 00833 } 00834 00835 //======================================================================================================================== 00836 void FSSROtsFirmware::sendTriggerNumberStripCSR(bool send) 00837 { 00838 BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) send, 25, 1); 00839 } 00840 00841 //======================================================================================================================== 00842 void FSSROtsFirmware::sendBCOStripCSR(bool send) 00843 { 00844 BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) send, 26, 1); 00845 } 00846 00847 //======================================================================================================================== 00848 void FSSROtsFirmware::enableStreamStripCSR(bool enable) 00849 { 00850 BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) enable, 27, 1); 00851 } 00852 00853 //======================================================================================================================== 00854 void FSSROtsFirmware::resetDCMStripCSR(bool clear) 00855 { 00856 BitManipulator::insertBits(stripCSRRegisterValue_, (uint32_t) clear, 31, 1); 00857 } 00858 00859 //======================================================================================================================== 00860 uint32_t FSSROtsFirmware::waitDCMResetStripCSR(void) 00861 { 00862 uint32_t bitToCheck = 0; 00863 BitManipulator::insertBits(bitToCheck, 1, 31, 2); 00864 return bitToCheck; 00865 } 00866 00867 //======================================================================================================================== 00868 void FSSROtsFirmware::resetDAC(void) 00869 { 00870 BitManipulator::insertBits(stripResetRegisterValue_, 1, 27, 1); 00871 } 00872 00873 //======================================================================================================================== 00874 void FSSROtsFirmware::resetLink(bool channel0, bool channel1, bool channel2, 00875 bool channel3, bool channel4, bool channel5) 00876 { 00877 stripResetRegisterValue_ = 0; 00878 BitManipulator::insertBits(stripResetRegisterValue_, 00879 ((uint32_t) channel0) + ((uint32_t) channel1 << 1) 00880 + ((uint32_t) channel2 << 2) + ((uint32_t) channel3 << 3) 00881 + ((uint32_t) channel4 << 4) + ((uint32_t) channel5 << 5), 00882 0, 6); 00883 BitManipulator::insertBits(stripResetRegisterValue_, 1, 29, 1); 00884 00885 // write(buffer, STRIP_RESET, (1<<28) + 00886 // ((uint32_t)channel0) + 00887 // ((uint32_t)channel1<<1) + 00888 // ((uint32_t)channel2<<2) + 00889 // ((uint32_t)channel3<<3) + 00890 // ((uint32_t)channel4<<4) + 00891 // ((uint32_t)channel5<<5) 00892 // ); 00893 00894 } 00895 00896 //======================================================================================================================== 00897 void FSSROtsFirmware::clearErrors(bool channel0, bool channel1, bool channel2, 00898 bool channel3, bool channel4, bool channel5) 00899 { 00900 stripResetRegisterValue_ = 0; 00901 BitManipulator::insertBits(stripResetRegisterValue_, 00902 ((uint32_t) channel0) + ((uint32_t) channel1 << 1) 00903 + ((uint32_t) channel2 << 2) + ((uint32_t) channel3 << 3) 00904 + ((uint32_t) channel4 << 4) + ((uint32_t) channel5 << 5), 00905 0, 6); 00906 BitManipulator::insertBits(stripResetRegisterValue_, 1, 29, 1); 00907 } 00908 00909 //======================================================================================================================== 00910 void FSSROtsFirmware::clearFIFO(bool channel0, bool channel1, bool channel2, 00911 bool channel3, bool channel4, bool channel5) 00912 { 00913 stripResetRegisterValue_ = 0; 00914 BitManipulator::insertBits(stripResetRegisterValue_, 00915 ((uint32_t) channel0) + ((uint32_t) channel1 << 1) 00916 + ((uint32_t) channel2 << 2) + ((uint32_t) channel3 << 3) 00917 + ((uint32_t) channel4 << 4) + ((uint32_t) channel5 << 5), 00918 0, 6); 00919 BitManipulator::insertBits(stripResetRegisterValue_, 1, 30, 1); 00920 } 00921 00922 //======================================================================================================================== 00923 void FSSROtsFirmware::resetChip(bool channel0, bool channel1, bool channel2, 00924 bool channel3, bool channel4, bool channel5) 00925 { 00926 stripResetRegisterValue_ = 0; 00927 BitManipulator::insertBits(stripResetRegisterValue_, 00928 ((uint32_t) channel0) + ((uint32_t) channel1 << 1) 00929 + ((uint32_t) channel2 << 2) + ((uint32_t) channel3 << 3) 00930 + ((uint32_t) channel4 << 4) + ((uint32_t) channel5 << 5), 00931 0, 6); 00932 BitManipulator::insertBits(stripResetRegisterValue_, 1, 31, 1); 00933 } 00934 00935 //======================================================================================================================== 00936 void FSSROtsFirmware::setFrequencyRatio(std::string& buffer, int numerator, int 00937 denominator) 00938 { 00939 //The device need to load numerator minus one and denominator minus one, with an 00940 internal address of 0x50 and 052 respectively OtsUDPFirmwareCore::write(buffer, 00941 STRIP_BCO_DCM, 0x80500000 + (numerator - 1)); // Set BCOCLK numerator // was 0x80500003 00942 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer, 00943 STRIP_BCO_DCM, 0xf0000000); // Wait DCM write to finish // was 0x80000000 00944 00945 OtsUDPFirmwareCore::write(buffer, STRIP_BCO_DCM, 0x80520000 + (denominator - 1)); // 00946 Set BCOCLK denominator // was 0x80520001 00947 //FIXME? Does Nothing RAR Aug 2017//OtsUDPFirmwareCore::waitClear(buffer, 00948 STRIP_BCO_DCM, 0xf0000000); // Wait DCM write to finish - BCO frequency should be 13.513 00949 MHz // was 0x80000000 00950 } 00951 00952 //======================================================================================================================== 00953 void FSSROtsFirmware::BCOOffset(uint32_t offset) 00954 { 00955 BitManipulator::insertBits(stripTriggerCSRRegisterValue_, offset, 0, 4); 00956 } 00957 00958 //======================================================================================================================== 00959 void FSSROtsFirmware::selectSpyFIFO(uint32_t input) 00960 { 00961 BitManipulator::insertBits(stripTriggerCSRRegisterValue_, input, 4, 3); 00962 } 00963 00964 //======================================================================================================================== 00965 void FSSROtsFirmware::halt(bool halt) 00966 { 00967 BitManipulator::insertBits(stripTriggerCSRRegisterValue_, (uint32_t) halt, 7, 1); 00968 } 00969 00970 //======================================================================================================================== 00971 void FSSROtsFirmware::configureStripTriggerUnbiased(std::string& buffer) 00972 { 00973 OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_UNBIASED, 0x002805c); // Configure 00974 unbiased trigger 00975 } 00976 00977 //======================================================================================================================== 00978 void FSSROtsFirmware::configureTriggerInputs(std::string& buffer) 00979 { 00980 OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_INPUT_0, 0x3f440000); // FSSR GOTHIT 00981 trigger input channel 0,1 OtsUDPFirmwareCore::write(buffer, STRIP_TRIG_INPUT_1, 00982 0x3f440000); // FSSR GOTHIT trigger input channel 2,3 OtsUDPFirmwareCore::write(buffer, 00983 STRIP_TRIG_INPUT_2, 0x0); // FSSR GOTHIT trigger input channel 4,5 00984 } 00985 00986 //======================================================================================================================== 00987 std::string FSSROtsFirmware::resetSlaveBCO(void) 00988 { 00989 std::string buffer; 00990 OtsUDPFirmwareCore::write(buffer, (uint64_t)0xc5000000, (uint64_t)0x00000008); 00991 return buffer; 00992 } 00993 00994 //======================================================================================================================== 00995 void FSSROtsFirmware::chipID(uint32_t size) 00996 { 00997 BitManipulator::insertBits(stripSCRegisterValue_, size, 0, 5); 00998 } 00999 01000 //======================================================================================================================== 01001 void FSSROtsFirmware::addressSlowControls(uint32_t size) 01002 { 01003 BitManipulator::insertBits(stripSCRegisterValue_, size, 5, 5); 01004 } 01005 01006 //======================================================================================================================== 01007 void FSSROtsFirmware::instructionSlowControls(uint32_t size) 01008 { 01009 BitManipulator::insertBits(stripSCRegisterValue_, size, 10, 3); 01010 } 01011 01012 //======================================================================================================================== 01013 void FSSROtsFirmware::channelreadSelect(uint32_t size) 01014 { 01015 BitManipulator::insertBits(stripSCRegisterValue_, size, 13, 3); 01016 } 01017 01018 //======================================================================================================================== 01019 void FSSROtsFirmware::channelMask(uint32_t size) 01020 { 01021 BitManipulator::insertBits(stripSCRegisterValue_, size, 16, 8); 01022 } 01023 01024 //======================================================================================================================== 01025 void FSSROtsFirmware::bitsLength(uint32_t length) 01026 { 01027 BitManipulator::insertBits(stripSCRegisterValue_, length, 26, 3); 01028 } 01029 01030 01031 //======================================================================================================================== 01032 void FSSROtsFirmware::syncFallingBCO(bool sync) 01033 { 01034 BitManipulator::insertBits(stripSCRegisterValue_, (uint32_t)sync, 28, 1); 01035 } 01036 01037 //======================================================================================================================== 01038 void FSSROtsFirmware::syncRisingBCO(bool sync) 01039 { 01040 BitManipulator::insertBits(stripSCRegisterValue_, (uint32_t)sync, 29, 1); 01041 } 01042 01043 //======================================================================================================================== 01044 void FSSROtsFirmware::setRaw(bool set) 01045 { 01046 BitManipulator::insertBits(stripSCRegisterValue_, (uint32_t)set, 30, 1); 01047 } 01048 01049 //======================================================================================================================== 01050 void FSSROtsFirmware::initSlowControls(bool init) 01051 { 01052 BitManipulator::insertBits(stripSCRegisterValue_, (uint32_t)init, 31, 1); 01053 } 01054 01055 //======================================================================================================================== 01056 void FSSROtsFirmware::resetCount(bool reset) 01057 { 01058 BitManipulator::insertBits(stripAnalysisCSRRegisterValue_, (uint32_t)reset, 30, 1); 01059 } 01060 01061 //======================================================================================================================== 01062 void FSSROtsFirmware::setBCO_0(uint32_t void FSSROtsFirmware::BCOOffset(uint32_t offset) 01063 { 01064 BitManipulator::insertBits(stripTrigCSRRegisterValue_, offset, 0, 4); 01065 }input) 01066 { 01067 BitManipulator::insertBits(trigInputRegisterValue_, input, 0, 8); 01068 } 01069 01070 //======================================================================================================================== 01071 void FSSROtsFirmware::setBCO_1(uint32_t input) 01072 { 01073 BitManipulator::insertBits(trigInputRegisterValue_, input, 8, 8); 01074 } 01075 01076 //======================================================================================================================== 01077 void FSSROtsFirmware::trimFracBCO_0(uint32_t input) 01078 { 01079 BitManipulator::insertBits(trigInputRegisterValue_, input, 16, 4); 01080 } 01081 01082 //======================================================================================================================== 01083 void FSSROtsFirmware::trimFracBCO_1(uint32_t input) 01084 { 01085 BitManipulator::insertBits(trigInputRegisterValue_, input, 20, 4); 01086 } 01087 01088 //======================================================================================================================== 01089 void FSSROtsFirmware::enable_0(bool enable) 01090 { 01091 BitManipulator::insertBits(trigInputRegisterValue_, (uint32_t)enable, 28, 1); 01092 } 01093 01094 //======================================================================================================================== 01095 void FSSROtsFirmware::enable_1(bool enable) 01096 { 01097 BitManipulator::insertBits(trigInputRegisterValue_, (uint32_t)enable, 29, 1); 01098 } 01099 01100 */