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00001 #ifndef _ots_PSI46DigFirmwareDefinitions_h 00002 #define _ots_PSI46DigFirmwareDefinitions_h 00003 00004 #include <stdint.h> 00005 00006 namespace ots 00007 { 00008 const uint64_t EnableSPIPixelNormalDataAddress = 0x300; 00009 // const UInt64 ChannelFIFOAddress[2] = {0x300,0x300}; 00010 00011 const uint32_t STRIP_CSR = 0xc4000000; 00012 const uint32_t STRIP_RESET = 0xc4000004; 00013 const uint32_t STRIP_SC_CSR = 0xc4000008; // Command/status register 00014 const uint32_t STRIP_SCI = 0xc4000010; // Write address for registers 00015 const uint32_t STRIP_SCI0 = 0xc4000010; // Write address for mask bits 00016 const uint32_t STRIP_SCI1 = 0xc4000014; // Write address for mask bits 00017 const uint32_t STRIP_SCI2 = 0xc4000018; // Write address for mask bits 00018 const uint32_t STRIP_SCI3 = 0xc400001c; // Write address for mask bits 00019 const uint32_t STRIP_SCO = 0xc4000020; // Read address for registers 00020 const uint32_t STRIP_SCO0 = 0xc4000020; // Read address for mask bits 00021 const uint32_t STRIP_SCO1 = 0xc4000024; // Read address for mask bits 00022 const uint32_t STRIP_SCO2 = 0xc4000028; // Read address for mask bits 00023 const uint32_t STRIP_SCO3 = 0xc400002c; // Read address for mask bits 00024 const uint32_t STRIP_FIFO_CSR = 0xc4000030; 00025 const uint32_t STRIP_FIFO_DATA = 0xc4000034; 00026 const uint32_t STRIP_ANALYSIS_CSR = 0xc4000038; 00027 const uint32_t STRIP_ANALYSIS_BCO_COUNTER = 0xc400003c; 00028 const uint32_t STRIP_ANALYSIS_CHIP1_HIT_COUNTER = 0xc400013c; 00029 const uint32_t STRIP_ANALYSIS_CHIP2_HIT_COUNTER = 0xc400023c; 00030 const uint32_t STRIP_ANALYSIS_CHIP3_HIT_COUNTER = 0xc400033c; 00031 const uint32_t STRIP_ANALYSIS_CHIP4_HIT_COUNTER = 0xc400043c; 00032 const uint32_t STRIP_ANALYSIS_CHIP5_HIT_COUNTER = 0xc400053c; 00033 const uint32_t STRIP_CHIP1_STATUS = 0xc4000130; 00034 const uint32_t STRIP_CHIP2_STATUS = 0xc4000230; 00035 const uint32_t STRIP_CHIP3_STATUS = 0xc4000330; 00036 const uint32_t STRIP_CHIP4_STATUS = 0xc4000430; 00037 const uint32_t STRIP_CHIP5_STATUS = 0xc4000530; 00038 const uint32_t STRIP_BCO_COUNTER_LOW = 0xc4000040; 00039 const uint32_t STRIP_BCO_COUNTER_HIGH = 0xc4000044; 00040 const uint32_t STRIP_BCO_DCM = 0xc4000048; 00041 // const uint32_t STRIP_STREAM_STATUS = 0xc400004c; 00042 const uint32_t STRIP_DAC_CSR = 0xc4000050; 00043 const uint32_t STRIP_DAC_INPUT = 0xc4000054; 00044 const uint32_t STRIP_DAC_SPI = 0xc4000058; 00045 // const uint32_t STRIP_WORDS_DUMPED = 0xc400005c; 00046 const uint32_t STRIP_TRIG_CSR = 0xc4000060; 00047 // const uint32_t STRIP_TRIG_FIFO_DATA = 0xc4000064; 00048 const uint32_t STRIP_TRIG_UNBIASED = 0xc4000068; 00049 const uint32_t STRIP_TRIG_INPUT_0 = 0xc4000070; 00050 const uint32_t STRIP_TRIG_INPUT_1 = 0xc4000074; 00051 const uint32_t STRIP_TRIG_INPUT_2 = 0xc4000078; 00052 const uint32_t STRIP_TRIG_INPUT_3 = 0xc400007c; 00053 // const uint32_t STRIP_TRIGNUM_LOW = 0xc4000080; 00054 // const uint32_t STRIP_TRIGNUM_HIGH = 0xc4000084; 00055 const uint32_t ETHIO_DESTINATION_PORT = 0xc1000018; 00056 const uint32_t DATA_DESTINATION_IP = 0xc10000a4; 00057 const uint32_t DATA_SOURCE_DESTINATION_PORT = 0xc10000a8; 00058 00059 const uint32_t STRIP_TRIM_CSR = 0xc4000088; 00060 const uint32_t STRIP_TLK_CSR = 0xc3000000; 00061 00062 const double EXTERNAL_CLOCK_FREQUENCY = 54; // base freq: 54MHz 00063 const double INTERNAL_CLOCK_FREQUENCY = 66.667; // base freq: 66.667MHz 00064 00065 const uint32_t ChannelFIFOAddress[6] = { 00066 STRIP_SCI, STRIP_SCI, STRIP_SCI, STRIP_SCI, STRIP_SCI, STRIP_SCI}; 00067 00068 const uint8_t WRITE = 1; 00069 const uint8_t SET = 2; 00070 const uint8_t READ = 4; 00071 const uint8_t RESET = 5; 00072 const uint8_t CLEAR = 5; 00073 const uint8_t DEFAULT = 6; 00074 const uint8_t WAITCLR = 7; 00075 const uint8_t WAITSET = 8; 00076 00077 const uint8_t STIB_DAC_WRITE_MAX = 22; 00078 } 00079 00080 #endif