00001 #ifndef ARTDAQ_DAQRATE_DATASENDERMANAGER_HH
00002 #define ARTDAQ_DAQRATE_DATASENDERMANAGER_HH
00003
00004 #include <map>
00005 #include <set>
00006 #include <memory>
00007 #include <netinet/in.h>
00008
00009 #include "fhiclcpp/fwd.h"
00010
00011 #include "artdaq-core/Data/Fragment.hh"
00012 #include "artdaq/TransferPlugins/TransferInterface.hh"
00013 #include "artdaq/DAQrate/detail/FragCounter.hh"
00014 #include "artdaq-utilities/Plugins/MetricManager.hh"
00015 #include "artdaq/DAQrate/detail/RoutingPacket.hh"
00016 #include "artdaq/TransferPlugins/detail/HostMap.hh"
00017 #include "fhiclcpp/types/Atom.h"
00018 #include "fhiclcpp/types/OptionalTable.h"
00019 #include "fhiclcpp/types/TableFragment.h"
00020
00021 namespace artdaq
00022 {
00023 class DataSenderManager;
00024 }
00025
00030 class artdaq::DataSenderManager
00031 {
00032 public:
00038 struct RoutingTableConfig
00039 {
00041 fhicl::Atom<bool> use_routing_master{ fhicl::Name{ "use_routing_master"}, fhicl::Comment{ "True if using the Routing Master"}, false };
00043 fhicl::Atom<int> table_port{ fhicl::Name{ "table_update_port"}, fhicl::Comment{ "Port that table updates should arrive on" },35556 };
00045 fhicl::Atom<std::string> table_address{ fhicl::Name{ "table_update_address"}, fhicl::Comment{ "Address that table updates should arrive on" }, "227.128.12.28" };
00047 fhicl::Atom<int> ack_port{ fhicl::Name{ "table_acknowledge_port" },fhicl::Comment{ "Port that acknowledgements should be sent to" },35557 };
00049 fhicl::Atom<std::string> ack_address{ fhicl::Name{ "routing_master_hostname"}, fhicl::Comment{ "Host that acknowledgements should be sent to" },"localhost" };
00051 fhicl::Atom<int> routing_timeout_ms{ fhicl::Name{"routing_timeout_ms"}, fhicl::Comment{"Time to wait (in ms) for a routing table update if the table is exhausted"}, 1000 };
00053 fhicl::Atom<int> routing_retry_count{ fhicl::Name{"routing_retry_count"}, fhicl::Comment{"Number of times to retry getting destination from routing table"}, 5 };
00054 };
00055
00059 struct DestinationsConfig
00060 {
00062 fhicl::OptionalTable<artdaq::TransferInterface::Config> dest{ fhicl::Name{"d1"}, fhicl::Comment{"Configuration for transfer to destination"} };
00063 };
00064
00068 struct Config
00069 {
00071 fhicl::Atom<bool> broadcast_sends{ fhicl::Name{"broadcast_sends"}, fhicl::Comment{"Send all Fragments to all destinations"}, false };
00073 fhicl::Atom<bool> nonblocking_sends{ fhicl::Name{"nonblocking_sends"}, fhicl::Comment{"Whether sends should block. Used for DL->DISP connection."}, false };
00075 fhicl::Atom<size_t> send_timeout_us{ fhicl::Name{"send_timeout_usec"}, fhicl::Comment{"Timeout for sends in non-reliable modes (broadcast and nonblocking)"},5000000 };
00077 fhicl::Atom<size_t> send_retry_count{ fhicl::Name{"send_retry_count"}, fhicl::Comment{"Number of times to retry a send in non-reliable mode"}, 2 };
00078 fhicl::OptionalTable<RoutingTableConfig> routing_table_config{ fhicl::Name{"routing_table_config"} };
00079
00080
00081 fhicl::OptionalTable<DestinationsConfig> destinations{ fhicl::Name{"destinations"} };
00082 fhicl::TableFragment<artdaq::HostMap::Config> host_map;
00083
00084 fhicl::Sequence<size_t> enabled_destinations{ fhicl::Name{"enabled_destinations"}, fhicl::Comment{"List of destiantion ranks to activate (must be defined in destinations block)"}, std::vector<size_t>() };
00085 };
00086 #if MESSAGEFACILITY_HEX_VERSION >= 0x20103
00087 using Parameters = fhicl::WrappedTable<Config>;
00088 #endif
00089
00094 explicit DataSenderManager(const fhicl::ParameterSet& ps);
00095
00099 virtual ~DataSenderManager();
00100
00106 std::pair<int, TransferInterface::CopyStatus> sendFragment(Fragment&& frag);
00107
00112 size_t count() const;
00113
00119 size_t slotCount(size_t rank) const;
00120
00125 size_t destinationCount() const { return destinations_.size(); }
00126
00131 std::set<int> enabled_destinations() const { return enabled_destinations_; }
00132
00137 size_t GetRoutingTableEntryCount() const;
00138 private:
00139
00140
00141 int calcDest_(Fragment::sequence_id_t) const;
00142
00143 void setupTableListener_();
00144
00145 void startTableReceiverThread_();
00146
00147 void receiveTableUpdatesLoop_();
00148 private:
00149
00150 std::map<int, std::unique_ptr<artdaq::TransferInterface>> destinations_;
00151 std::unordered_map<int, std::pair<size_t, double>> destination_metric_data_;
00152 std::unordered_map<int, std::chrono::steady_clock::time_point> destination_metric_send_time_;
00153 std::set<int> enabled_destinations_;
00154
00155 detail::FragCounter sent_frag_count_;
00156
00157 bool broadcast_sends_;
00158 bool non_blocking_mode_;
00159 size_t send_timeout_us_;
00160 size_t send_retry_count_;
00161
00162 bool use_routing_master_;
00163 detail::RoutingMasterMode routing_master_mode_;
00164 std::atomic<bool> should_stop_;
00165 int table_port_;
00166 std::string table_address_;
00167 int ack_port_;
00168 std::string ack_address_;
00169 struct sockaddr_in ack_addr_;
00170 int ack_socket_;
00171 int table_socket_;
00172 std::map<Fragment::sequence_id_t, int> routing_table_;
00173 mutable std::mutex routing_mutex_;
00174 boost::thread routing_thread_;
00175 mutable std::atomic<size_t> routing_wait_time_;
00176
00177 int routing_timeout_ms_;
00178 int routing_retry_count_;
00179 };
00180
00181 inline
00182 size_t
00183 artdaq::DataSenderManager::
00184 count() const
00185 {
00186 return sent_frag_count_.count();
00187 }
00188
00189 inline
00190 size_t
00191 artdaq::DataSenderManager::
00192 slotCount(size_t rank) const
00193 {
00194 return sent_frag_count_.slotCount(rank);
00195 }
00196 #endif //ARTDAQ_DAQRATE_DATASENDERMANAGER_HH