00001 #ifndef ARTDAQ_DAQRATE_DATASENDERMANAGER_HH
00002 #define ARTDAQ_DAQRATE_DATASENDERMANAGER_HH
00003
00004 #include <map>
00005 #include <set>
00006 #include <memory>
00007 #include <netinet/in.h>
00008
00009 #include "fhiclcpp/fwd.h"
00010
00011 #include "artdaq-core/Data/Fragment.hh"
00012 #include "artdaq/TransferPlugins/TransferInterface.hh"
00013 #include "artdaq/DAQrate/detail/FragCounter.hh"
00014 #include "artdaq-utilities/Plugins/MetricManager.hh"
00015 #include "artdaq/DAQrate/detail/RoutingPacket.hh"
00016 #include "artdaq/TransferPlugins/detail/HostMap.hh"
00017 #include "fhiclcpp/types/Atom.h"
00018 #include "fhiclcpp/types/OptionalTable.h"
00019 #include "fhiclcpp/types/TableFragment.h"
00020
00021 namespace artdaq
00022 {
00023 class DataSenderManager;
00024 }
00025
00030 class artdaq::DataSenderManager
00031 {
00032 public:
00033
00034 struct RoutingTableConfig
00035 {
00036 fhicl::Atom<bool> use_routing_master{ fhicl::Name{ "use_routing_master"}, fhicl::Comment{ "True if using the Routing Master"}, false };
00037 fhicl::Atom<int> table_port{ fhicl::Name{ "table_update_port"}, fhicl::Comment{ "Port that table updates should arrive on" },35556 };
00038 fhicl::Atom<std::string> table_address{ fhicl::Name{ "table_update_address"}, fhicl::Comment{ "Address that table updates should arrive on" }, "227.128.12.28" };
00039 fhicl::Atom<int> ack_port{ fhicl::Name{ "table_acknowledge_port" },fhicl::Comment{ "Port that acknowledgements should be sent to" },35557 };
00040 fhicl::Atom<std::string> ack_address{ fhicl::Name{ "routing_master_hostname"}, fhicl::Comment{ "Host that acknowledgements should be sent to" },"localhost" };
00041 fhicl::Atom<int> routing_timeout_ms{ fhicl::Name{"routing_timeout_ms"}, fhicl::Comment{"Time to wait (in ms) for a routing table update if the table is exhausted"}, 1000 };
00042 fhicl::Atom<int> routing_retry_count{ fhicl::Name{"routing_retry_count"}, fhicl::Comment{"Number of times to retry getting destination from routing table"}, 5 };
00043 };
00044
00045 struct DestinationsConfig
00046 {
00047 fhicl::OptionalTable<artdaq::TransferInterface::Config> dest{ fhicl::Name{"d1"}, fhicl::Comment{"Configuration for transfer to destination"} };
00048 };
00049
00050 struct Config
00051 {
00052 fhicl::Atom<bool> broadcast_sends{ fhicl::Name{"broadcast_sends"}, fhicl::Comment{"Send all Fragments to all destinations"}, false };
00053 fhicl::Atom<bool> nonblocking_sends{ fhicl::Name{"nonblocking_sends"}, fhicl::Comment{"Whether sends should block. Used for DL->DISP connection."}, false };
00054 fhicl::Atom<size_t> send_timeout_us{ fhicl::Name{"send_timeout_usec"}, fhicl::Comment{"Timeout for sends in non-reliable modes (broadcast and nonblocking)"},5000000 };
00055 fhicl::Atom<size_t> send_retry_count{ fhicl::Name{"send_retry_count"}, fhicl::Comment{"Number of times to retry a send in non-reliable mode"}, 2 };
00056 fhicl::OptionalTable<RoutingTableConfig> routing_table_config{ fhicl::Name{"routing_table_config"} };
00057 fhicl::OptionalTable<DestinationsConfig> destinations{ fhicl::Name{"destinations"} };
00058 fhicl::TableFragment<artdaq::HostMap::Config> host_map;
00059 fhicl::Sequence<size_t> enabled_destinations{ fhicl::Name{"enabled_destinations"}, fhicl::Comment{"List of destiantion ranks to activate (must be defined in destinations block)"}, std::vector<size_t>() };
00060 };
00061 #if MESSAGEFACILITY_HEX_VERSION >= 0x20103
00062 using Parameters = fhicl::WrappedTable<Config>;
00063 #endif
00064
00089 explicit DataSenderManager(const fhicl::ParameterSet& ps);
00090
00094 virtual ~DataSenderManager();
00095
00101 std::pair<int, TransferInterface::CopyStatus> sendFragment(Fragment&& frag);
00102
00107 size_t count() const;
00108
00114 size_t slotCount(size_t rank) const;
00115
00120 size_t destinationCount() const { return destinations_.size(); }
00121
00126 std::set<int> enabled_destinations() const { return enabled_destinations_; }
00127
00132 size_t GetRoutingTableEntryCount() const;
00133 private:
00134
00135
00136 int calcDest_(Fragment::sequence_id_t) const;
00137
00138 void setupTableListener_();
00139
00140 void startTableReceiverThread_();
00141
00142 void receiveTableUpdatesLoop_();
00143 private:
00144
00145 std::map<int, std::unique_ptr<artdaq::TransferInterface>> destinations_;
00146 std::set<int> enabled_destinations_;
00147
00148 detail::FragCounter sent_frag_count_;
00149
00150 bool broadcast_sends_;
00151 bool non_blocking_mode_;
00152 size_t send_timeout_us_;
00153 size_t send_retry_count_;
00154
00155 bool use_routing_master_;
00156 detail::RoutingMasterMode routing_master_mode_;
00157 std::atomic<bool> should_stop_;
00158 int table_port_;
00159 std::string table_address_;
00160 int ack_port_;
00161 std::string ack_address_;
00162 struct sockaddr_in ack_addr_;
00163 int ack_socket_;
00164 int table_socket_;
00165 std::map<Fragment::sequence_id_t, int> routing_table_;
00166 mutable std::mutex routing_mutex_;
00167 boost::thread routing_thread_;
00168 mutable std::atomic<size_t> routing_wait_time_;
00169
00170 int routing_timeout_ms_;
00171 int routing_retry_count_;
00172 };
00173
00174 inline
00175 size_t
00176 artdaq::DataSenderManager::
00177 count() const
00178 {
00179 return sent_frag_count_.count();
00180 }
00181
00182 inline
00183 size_t
00184 artdaq::DataSenderManager::
00185 slotCount(size_t rank) const
00186 {
00187 return sent_frag_count_.slotCount(rank);
00188 }
00189 #endif //ARTDAQ_DAQRATE_DATASENDERMANAGER_HH